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path: root/drivers/clk/renesas
AgeCommit message (Expand)Author
5 daysReplace <linux/mod_devicetable.h> by more specific <linux/device-id/*.h> (c f...Uwe Kleine-König (The Capable Hub)
2026-05-28clk: renesas: r9a08g045: Drop unused pm_domain header fileBiju Das
2026-05-28clk: renesas: r8a779g0: Add DSC clockMarek Vasut
2026-05-25clk: renesas: rzg2l: Rename iterator in for_each_mod_clock() to avoid shadowingLad Prabhakar
2026-05-25clk: renesas: r9a08g045: Drop unused DEF_G3S_MUX macroLad Prabhakar
2026-05-22clk: renesas: rzg2l: Rename RZG3L-prefixed PLL macros to CPG-prefixed onesBiju Das
2026-05-22clk: renesas: rzg3s/rzg3l: Simplify PLL configuration macroBiju Das
2026-05-22clk: renesas: rzg2l: Simplify SAM PLL configuration macroBiju Das
2026-05-15clk: renesas: r8a73a4: Add ZT/ZTR trace clocksMarek Vasut
2026-05-11clk: renesas: r9a08g046: Add RSPI clocks and resetsBiju Das
2026-05-11clk: renesas: r9a08g046: Add SSIF-2 clocks and resetsBiju Das
2026-05-11clk: renesas: r9a08g046: Add RSCI clocks and resetsBiju Das
2026-05-07clk: renesas: cpg-mssr: Add number of clock cells checkGeert Uytterhoeven
2026-05-07clk: renesas: rzg2l: Refactor rzg3l_cpg_pll_clk_endisable()Geert Uytterhoeven
2026-05-07clk: renesas: rzg2l: Consolidate DEF_MUX() and DEF_MUX_FLAGS()Geert Uytterhoeven
2026-05-07clk: renesas: r9a08g046: Add IA55_PCLK to critical module clocksBiju Das
2026-05-04Merge tag 'clk-renesas-rzg3e-plldsi-tag' into renesas-clk-for-v7.2Geert Uytterhoeven
2026-05-04clk: renesas: r9a09g047: Add support for LCDC{0,1} clocks and resetsTommaso Merciai
2026-05-04clk: renesas: r9a09g047: Add support for DSI clocks and resetsTommaso Merciai
2026-05-04clk: renesas: r9a09g047: Add support for SMUX2_DSI{0,1}_CLKTommaso Merciai
2026-05-04clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_CSDIV clocksTommaso Merciai
2026-05-04clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_DIV7 clocksTommaso Merciai
2026-05-04clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1} clocksTommaso Merciai
2026-05-04clk: renesas: r9a09g047: Add CLK_PLLETH_LPCLK supportTommaso Merciai
2026-05-04clk: renesas: rzv2h: Add PLLDSI clk mux supportTommaso Merciai
2026-04-27clk: renesas: r8a7740: Add ZT/ZTR trace clocksMarek Vasut
2026-04-27clk: renesas: r9a09g077: Add MTU3 module clockCosmin Tanislav
2026-04-27clk: renesas: r9a08g046: Add I2C clocks and resetsBiju Das
2026-04-27clk: renesas: r9a08g046: Add SCIF{1..5} clocks and resetsBiju Das
2026-04-27clk: renesas: r9a08g046: Add WDT clocks and resetBiju Das
2026-04-27clk: renesas: r9a08g046: Add CA55 core clocksBiju Das
2026-04-27clk: renesas: r9a08g046: Add GPIO clocks/resetsBiju Das
2026-04-27clk: renesas: r9a08g046: Add GBETH clocks and resetsBiju Das
2026-04-27clk: renesas: r8a08g046: Add support for PLL6Biju Das
2026-04-27clk: renesas: rzg2l: Add support for enabling PLLsBiju Das
2026-04-27clk: renesas: rzg2l: Drop always-false check in rzg3s_cpg_pll_clk_recalc_rate()Biju Das
2026-03-26clk: renesas: Add support for RZ/G3L SoCBiju Das
2026-03-26clk: renesas: rzg2l: Re-enable critical module clocks during resumeBiju Das
2026-03-26clk: renesas: rzg2l: Add rzg2l_mod_clock_init_mstop_helper()Biju Das
2026-03-26clk: renesas: rzg2l: Add helper for mod clock enable/disableBiju Das
2026-03-26clk: renesas: r9a0{7g04[34],8g045}: Add critical reset entriesBiju Das
2026-03-26clk: renesas: rzg2l: Add support for critical resetsBiju Das
2026-03-25clk: renesas: r9a09g056: Remove entries for WDT{0,2,3}Fabrizio Castro
2026-03-25clk: renesas: r9a06g032: Enable watchdog reset sourcesHerve Codina (Schneider Electric)
2026-03-25clk: renesas: cpg-mssr: Use struct_size() helperRosen Penev
2026-03-20clk: renesas: r9a09g047: Add PCIe clocks and resetJohn Madieu
2026-03-20clk: renesas: r9a09g057: Add PCIe clocks and resetLad Prabhakar
2026-03-20clk: renesas: r9a09g056: Add PCIe clocks and resetLad Prabhakar
2026-03-20clk: renesas: r9a09g047: Add entries for the RSPIsTommaso Merciai
2026-03-06clk: renesas: r9a09g056: Add clock and reset entries for RTCOvidiu Panait