| Age | Commit message (Collapse) | Author |
|---|
|
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"Mostly the usual clk driver updates and new SoC additions plus
non-critical data fixes for things that weren't used yet.
One thing that's new here in the core is SSC spread spectrum support
(SSC) in the clk provider API. The idea is that DT authors will
configure SSC for certain clks and they'll be configured at clk
provider registration time or when a consumer device is probed,
similar to how we handle assigned clk rates or parents.
On the clk driver side we have Qualcomm adding almost half the diff
because they add support for 4 different SoCs and then a long tail of
other SoCs like Mediatek, Renesas, Rockchip, SpaceMiT, etc. add more
SoC support this time around. Luckily it's mostly clk data for these
new SoCs because the actual clk_ops are already there. Beyond the new
drivers we get all the little fixups for more compilation coverage or
usage of more modern APIs. That all looks normal.
Finally, I kinda buried the lede, I'm bringing on Brian and Jerome to
help out with maintaining the clk subsystem. The current working model
is already semi-distributed in that silicon vendors typically take
care of their drivers and send me pull requests but I'm becoming a
bottleneck for new drivers and core framework review because this has
become a 100% volunteer effort on my part.
Mike is stepping down after all these years (thanks Mike!) and that
jump started the conversation around finding co-maintainers. Brian and
Jerome have graciously offered to help me with the work load, meaning
in the future they'll be sending pull requests and committing directly
to the clk.git tree. They've both been around on the list for a while,
I've met them both in person, and they've been making changes to the
core clk framework along with helping review patches so I'm pretty
confident this will work well.
Core:
- devm_clk_bulk_get_enable() consumer API
- devm_clk_hw_register_composite_pdata() provider API
- Spread Spectrum Clock (SSC) support via DT bindings and provider APIs
- Divider clk rounding improved (and tested)
New Drivers:
- Cix Sky1 audio subsystem (AUDSS)
- UltraRISC DP1000
- MediaTek MT8173 MFG_TOP
- Si549
- Aspeed AST2700 PECI
- Airoha EN7523 PCIe
- Rockchip RV1106
- Mobileye EyeQ7H
- Qualcomm Maili GCC, TCSR, RPMh, and video clks
- Qualcomm Shikra GCC, RPM, GPU, display, and audio clks
- Qualcomm Nord display and graphics clks
- Qualcomm Glymur camera and EVA clks
- Qualcomm Hawi video clks
- Amlogic A9 AO and peripheral clks
- Renesas R-Car X5H (R8A78000) CPG"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (269 commits)
clk: microchip: mpfs: fix regmap_update_bits() mask/val order
clk: visconti: Make sure clk_init_data is fully initialized
clk: ti: Make sure clk_init_data is fully initialized
MAINTAINERS: Add Brian Masney and Jerome Brunet as co-maintainers for clk subsystem
Drop Michael Turquette's clk maintainer entry
clk: ti: composite: resolve parent clocks by DT index, not by name
clk: ti: mux: resolve parent clocks by DT index, not by name
clk: devres: fix cleanup in devm_clk_get_optional_enabled_with_rate()
dt-bindings: clock: ti,keystone-gate: Convert to DT schema
dt-bindings: clock: ti: Convert APLL clock to DT schema
clk: zynq: pll: Fix kernel-doc after determine_rate() conversion
dt-bindings: clock: ti,clockdomain: Convert to DT schema
dt-bindings: clock: Correct white-space style
clk: samsung: Don't include <linux/mod_devicetable.h>
clk: at91: Read "reg" with helper
clk: renesas: Add R-Car X5H CPG driver
clk: rockchip: rk3576: fix source muxes for SPI0..SPI4
clk: rockchip: Add clock controller for the RV1106
dt-bindings: clock: rockchip: Add RV1106 CRU support
dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator
...
|
|
The i2s{0,2,3,4,5}_sysclk_div DDNs have an additional fixed 1/2
divider in the hardware IP after the configurable divider, so the
real output rate is:
rate = parent_rate * den / (num * 2)
Set pre_div to 2 to account for it.
Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree")
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260717-k3-clk-fix-i2s-v1-3-e95001a692ee@linux.spacemit.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
|
|
The K3 i2s clocks were modelled as a single path behind one MPMU
register:
pll1_d96_25p6 / i2s_153p6_base
`-- i2s_sysclk_src (mux+gate, MPMU_ISCCR)
`-- i2s1_sysclk (DDN, MPMU_ISCCR)
|-- i2s_bclk (div+gate, MPMU_ISCCR)
`-- i2s2_sysclk (mux, parent 0)
The hardware actually has two i2s clock control registers, ISCCR0
(0x0040) and ISCCR1 (0x0044): ISCCR1 drives the common sysclk shared
by i2s0/2/3/4/5 and the common bclk, whose divider always implies a
fixed 1/2 factor in front, while ISCCR0 drives a dedicated path for
i2s1:
pll1_d96_25p6 / i2s_153p6_base
|-- i2s_sysclk_src (mux+gate, MPMU_ISCCR1)
| `-- i2s_sysclk (DDN, MPMU_ISCCR1)
| |-- i2s_bclk_factor (fixed factor, /2)
| | `-- i2s_bclk (div+gate, MPMU_ISCCR1)
| `-- i2s2_sysclk (mux, parent 0)
`-- i2s1_sysclk_src (mux+gate, MPMU_ISCCR0)
`-- i2s1_sysclk (DDN, MPMU_ISCCR0)
Because of this mismatch, i2s_bclk reported twice the real rate, and
the dedicated i2s1 clock path could not be described in DT at all.
Model the tree as above: split the MPMU_ISCCR register macro into
MPMU_ISCCR0 and MPMU_ISCCR1 to match the hardware register names,
rename the common DDN to i2s_sysclk, insert the fixed 1/2 factor
i2s_bclk_factor in front of i2s_bclk, and add the i2s1_sysclk_src mux
and i2s1_sysclk DDN backed by MPMU_ISCCR0. CLK_MPMU_I2S1_SYSCLK now
refers to the dedicated i2s1 clock; no in-tree user references this
ID, so nothing is affected by the change of meaning.
Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree")
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260717-k3-clk-fix-i2s-v1-2-e95001a692ee@linux.spacemit.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
|
|
Add the UFS reference clock for SpacemiT K3 SoC.
Link: https://patch.msgid.link/20260630-06-clk-ufs-support-v1-3-cf7521d1d0fe@kernel.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
|
|
According to SpacemiT updated clock docs, the previous UFS aclk parent
clock was wrong, the correct one is illustrated below, so fix it.
--> pll1_d5_491p52 --\
--> pll1_d6_409p6 --|
--> pll2_d6 --|--> div --> gate --> ufs_aclk
--> pll2_d5 --/
Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree")
Link: https://patch.msgid.link/20260630-06-clk-ufs-support-v1-1-cf7521d1d0fe@kernel.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
|
|
HDMA clock is responsible for the internal TCM access path of X100 RISC-V
core, so set the clock flag as critical to prevent it from being shut off,
otherwise the Linux system will hang, for example in the case of a vector
instruction access generates a page fault.
Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree")
Reported-by: Han Gao <gaohan@iscas.ac.cn>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Link: https://patch.msgid.link/20260630-06-clk-hdma-critial-v1-1-443c0ac88c5f@kernel.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
|
|
According to SpacemiT K3's updated docs, the USB2 ahb reset and USB2 bus
clock enable bit was wrongly swapped, the correct one should be:
Register : APMU_USB_CLK_RES_CTRL
bit[1] : usb2_port_bus_clk_en
bit[0] : usb2_port_ahb_rstn
Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree")
Reported-by: Junzhong Pan <panjunzhong@linux.spacemit.com>
Link: https://patch.msgid.link/20260518-06-clk-reset-usb-fix-v1-1-14fc235e692b@kernel.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
|
|
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"This is all clk driver updates. Mostly new SoC support for various
Qualcomm chips and Canaan K230. Otherwise there's non-critical fixes
and updates to clk data such as adding missing clks to existing
drivers or marking clks critical. Nothing looks especially exciting"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (106 commits)
clk: qcom: regmap-phy-mux: Rework the implementation
clk: qcom: a53: Corrected frequency multiplier for 1152MHz
clk: qcom: camcc-milos: Declare icc path dependency for CAMSS_TOP_GDSC
clk: qcom: gdsc: Support enabling interconnect path for power domain
dt-bindings: clock: qcom,milos-camcc: Document interconnect path
interconnect: Add devm_of_icc_get_by_index() as exported API for users
clk: qcom: camcc-x1p42100: Add support for camera clock controller
clk: qcom: camcc-x1e80100: Add support for camera QDSS debug clocks
clk: qcom: videocc-x1p42100: Add support for video clock controller
dt-bindings: clock: qcom: Add X1P42100 camera clock controller
dt-bindings: clock: qcom: Add X1P42100 video clock controller
clk: keystone: sci-clk: fix application of sizeof to pointer
clk: keystone: don't cache clock rate
clk: spacemit: k3: Add PCIe DBI clock
dt-bindings: soc: spacemit: k3: Add PCIe DBI clock IDs
clk: spacemit: k3: Fix PCIe clock register offset
clk: spacemit: k3: Switch to pll2_d6 as parent for PCIe clock
clk: at91: keep securam node alive while mapping it
clk: samsung: exynos990: Fix PERIC0/1 USI clock types
clk: renesas: r9a08g045: Drop unused pm_domain header file
...
|
|
Add PCIe DBI (Data Bus Interface) clock which was missing, This will
support PCIe driver to explicitly request and enable all clocks that
needed.
Link: https://patch.msgid.link/20260511-06-pci-clk-fix-v2-4-c9a5e563bab3@kernel.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
|
|
According to SpacemiT updated docs, the PCIe master and slave clock's
parent is the pll2_d6 clock, so fix it.
Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree")
Link: https://patch.msgid.link/20260511-06-pci-clk-fix-v2-1-c9a5e563bab3@kernel.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
|
|
top_dclk is the DDR bus clock. If it is gated by clk_disable_unused,
all memory-mapped bus transactions cease to function, causing DMA
engines to hang and general system instability.
Mark it CLK_IS_CRITICAL so the CCF never gates it during the
unused clock sweep.
Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree")
Reviewed-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
Fix inverted condition that skips frequency change trigger,
causing kernel panics during cpufreq scaling.
Fixes: 1b72c59db0ad ("clk: spacemit: Add clock support for SpacemiT K1 SoC")
Signed-off-by: Shuwei Wu <shuwei.wu@mailbox.org>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260305-k1-clk-fix-v1-1-abca85d6e266@mailbox.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
|
|
This was done entirely with mindless brute force, using
git grep -l '\<k[vmz]*alloc_objs*(.*, GFP_KERNEL)' |
xargs sed -i 's/\(alloc_objs*(.*\), GFP_KERNEL)/\1)/'
to convert the new alloc_obj() users that had a simple GFP_KERNEL
argument to just drop that argument.
Note that due to the extreme simplicity of the scripting, any slightly
more complex cases spread over multiple lines would not be triggered:
they definitely exist, but this covers the vast bulk of the cases, and
the resulting diff is also then easier to check automatically.
For the same reason the 'flex' versions will be done as a separate
conversion.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
|
|
This is the result of running the Coccinelle script from
scripts/coccinelle/api/kmalloc_objs.cocci. The script is designed to
avoid scalar types (which need careful case-by-case checking), and
instead replace kmalloc-family calls that allocate struct or union
object instances:
Single allocations: kmalloc(sizeof(TYPE), ...)
are replaced with: kmalloc_obj(TYPE, ...)
Array allocations: kmalloc_array(COUNT, sizeof(TYPE), ...)
are replaced with: kmalloc_objs(TYPE, COUNT, ...)
Flex array allocations: kmalloc(struct_size(PTR, FAM, COUNT), ...)
are replaced with: kmalloc_flex(*PTR, FAM, COUNT, ...)
(where TYPE may also be *VAR)
The resulting allocations no longer return "void *", instead returning
"TYPE *".
Signed-off-by: Kees Cook <kees@kernel.org>
|
|
Add clock support to SpacemiT K3 SoC, the clock tree consist of several
blocks which are APBC, APBS, APMU, DCIU, MPUM.
Link: https://lore.kernel.org/r/20260108-k3-clk-v5-5-42a11b74ad58@gentoo.org
Signed-off-by: Yixun Lan <dlan@gentoo.org>
|
|
Introduce a new clock PLLA for SpacemiT's K3 SoC which has a different
register layout comparing to previous PPL type. And, It is configured
by swcr1, swcr3 and swcr2 BIT[15:8].
Link: https://lore.kernel.org/r/20260108-k3-clk-v5-3-42a11b74ad58@gentoo.org
Signed-off-by: Yixun Lan <dlan@gentoo.org>
|
|
K3 SoC has the clock IP which support to write value 0 for enabling the
clock, while write 1 for disabling it, thus the enable BIT is inverted.
So, introduce a flag to support the inverted gate clock.
Link: https://lore.kernel.org/r/20260108-k3-clk-v5-2-42a11b74ad58@gentoo.org
Signed-off-by: Yixun Lan <dlan@gentoo.org>
|
|
This change is needed for adding future new SpacemiT K3 reset driver.
Since both K1 and K3 reset code register via the same module which its
name changed to spacemit_ccu, it's necessary to encode the platform/SoC
in the reset auxiliary device name to distinguish them, otherwise two
reset drivers will claim to support same "compatible" auxiliary device
even in the case of only one CCU clock driver got registered, which in
the end lead to a broken reset driver.
This change will introduce a runtime break to reset driver, and will be
fixed in follow-up commit:
ecff77f7c041 ("reset: spacemit: fix auxiliary device id")
Link: https://lore.kernel.org/r/20260108-06-k1-clk-common-v4-3-badf635993d3@gentoo.org
Reviewed-by: Alex Elder <elder@riscstar.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
|
|
Refactor the probe function of SpacemiT's clock, and extract a common ccu
file, so new clock driver added in the future can share the same code,
which would lower the burden of maintenance. Since this commit changes the
module name from spacemit_ccu_k1 to spacemit_ccu where the auxiliary device
registered, the auxiliary device id need to be adjusted. Idea of the patch
comes from the review of K3 clock driver, please refer to this disucssion[1]
for more detail.
This change will introduce a runtime break to reset driver, and will be
fixed in follow-up commit:
ecff77f7c041 ("reset: spacemit: fix auxiliary device id")
Link: https://lore.kernel.org/all/aTo8sCPpVM1o9PKX@pie/ [1]
Link: https://lore.kernel.org/r/20260108-06-k1-clk-common-v4-2-badf635993d3@gentoo.org
Suggested-by: Yao Zi <me@ziyao.cc>
Reviewed-by: Alex Elder <elder@riscstar.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
|
|
Since the common clock driver is only a dependency for other spacemit
clock driver, it should not be enabled individually, so hide this in
the Kconfig UI and let other spacemit clock driver select it.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20251219012819.440972-3-inochiama@gmail.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>
|
|
Currently, the SPACEMIT_CCU entry is only a switch for enabling entry
SPACEMIT_K1_CCU. It does not guide the build for common clock codes
even if it is a tristate entry. This makes this entry useless.
Change the Makefile to add a separate build for common clock logic,
so the SPACEMIT_CCU entry takes effect, also add necessary
MODULE_LICENSE()/MODULE_DESCRIPTION()/EXPORT_SYMBOL() for the module
build.
Fixes: 1b72c59db0ad ("clk: spacemit: Add clock support for SpacemiT K1 SoC")
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20251219012819.440972-2-inochiama@gmail.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>
|
|
When booting with KASAN enabled the following splat is
encountered during probe of the k1 clock driver:
UBSAN: array-index-out-of-bounds in drivers/clk/spacemit/ccu-k1.c:1044:16
index 0 is out of range for type 'clk_hw *[*]'
CPU: 0 UID: 0 PID: 1 Comm: swapper/0 Not tainted 6.18.0-rc5+ #1 PREEMPT(lazy)
Hardware name: Unknown Unknown Product/Unknown Product, BIOS 2022.10spacemit 10/01/2022
Call Trace:
[<ffffffff8002b628>] dump_backtrace+0x28/0x38
[<ffffffff800027d2>] show_stack+0x3a/0x50
[<ffffffff800220c2>] dump_stack_lvl+0x5a/0x80
[<ffffffff80022100>] dump_stack+0x18/0x20
[<ffffffff800164b8>] ubsan_epilogue+0x10/0x48
[<ffffffff8099034e>] __ubsan_handle_out_of_bounds+0xa6/0xa8
[<ffffffff80acbfa6>] k1_ccu_probe+0x37e/0x420
[<ffffffff80b79e6e>] platform_probe+0x56/0x98
[<ffffffff80b76a7e>] really_probe+0x9e/0x350
[<ffffffff80b76db0>] __driver_probe_device+0x80/0x138
[<ffffffff80b76f52>] driver_probe_device+0x3a/0xd0
[<ffffffff80b771c4>] __driver_attach+0xac/0x1b8
[<ffffffff80b742fc>] bus_for_each_dev+0x6c/0xc8
[<ffffffff80b76296>] driver_attach+0x26/0x38
[<ffffffff80b759ae>] bus_add_driver+0x13e/0x268
[<ffffffff80b7836a>] driver_register+0x52/0x100
[<ffffffff80b79a78>] __platform_driver_register+0x28/0x38
[<ffffffff814585da>] k1_ccu_driver_init+0x22/0x38
[<ffffffff80023a8a>] do_one_initcall+0x62/0x2a0
[<ffffffff81401c60>] do_initcalls+0x170/0x1a8
[<ffffffff81401e7a>] kernel_init_freeable+0x16a/0x1e0
[<ffffffff811f7534>] kernel_init+0x2c/0x180
[<ffffffff80025f56>] ret_from_fork_kernel+0x16/0x1d8
[<ffffffff81205336>] ret_from_fork_kernel_asm+0x16/0x18
---[ end trace ]---
This is bogus and is simply a result of KASAN consulting the
`.num` member of the struct for bounds information (as it should
due to `__counted_by`) and finding 0 set by kzalloc() because it
has not been initialized before the loop that fills in the array.
The easy fix is to just move the line that sets `num` to before
the loop that fills the array so that KASAN has the information
it needs to accurately conclude that the access is valid.
Fixes: 1b72c59db0add ("clk: spacemit: Add clock support for SpacemiT K1 SoC")
Tested-by: Yanko Kaneti <yaneti@declera.com>
Signed-off-by: Charles Mirabile <cmirabil@redhat.com>
Reviewed-by: Alex Elder <elder@riscstar.com>
Reviewed-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
Fix incorrect comment to match the filename.
Reviewd-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Signed-off-by: Encrow Thorne <jyc0019@gmail.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
Defining i2s_bclk and i2s_sysclk as fixed-rate clocks is insufficient
for real I2S use cases.
Moreover, the current I2S clock configuration does not work as expected
due to missing parent clocks.
This patch adds the missing parent clocks, defines i2s_sysclk as
a DDN clock, and i2s_bclk as a DIV clock.
A special note for i2s_bclk:
From the register definition, the i2s_bclk divider always implies
an additional 1/2 factor.
The following table shows the correspondence between index
and frequency division coefficients:
| index | div |
|-------|-------|
| 0 | 2 |
| 1 | 4 |
| 2 | 6 |
| 3 | 8 |
From a software perspective, introducing i2s_bclk_factor as the
parent of i2s_bclk is sufficient to address the issue.
The I2S-related clock registers can be found here [1].
Link:
https://developer.spacemit.com/documentation?token=LCrKwWDasiJuROkVNusc2pWTnEb
[1]
Fixes: 1b72c59db0add ("clk: spacemit: Add clock support for SpacemiT K1 SoC")
Co-developer: Jinmei Wei <weijinmei@linux.spacemit.com>
Suggested-by: Haylen Chu <heylenay@4d2.org>
Signed-off-by: Jinmei Wei <weijinmei@linux.spacemit.com>
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
The original DDN operations applied an implicit divide-by-2, which should
not be a default behavior.
This patch removes that assumption, letting each clock define its
actual behavior explicitly.
Reviewed-by: Haylen Chu <heylenay@4d2.org>
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Signed-off-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Haylen Chu <heylenay@4d2.org>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20250811-clk-for-stephen-round-rate-v1-51-b3bf97b038dc@redhat.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>
|
|
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Signed-off-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Haylen Chu <heylenay@4d2.org>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20250811-clk-for-stephen-round-rate-v1-50-b3bf97b038dc@redhat.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>
|
|
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Signed-off-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Haylen Chu <heylenay@4d2.org>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20250811-clk-for-stephen-round-rate-v1-49-b3bf97b038dc@redhat.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>
|
|
Hardware Requirement:
BIT[3] of this register must be set if need to select i2s_bclk as
SSPA parent clock, to solve this, introduces a new SSPAx_I2S_BCLK
clock as the virtual gate clock.
Fixes: 1b72c59db0add ("clk: spacemit: Add clock support for SpacemiT K1 SoC")
Suggested-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Haylen Chu <heylenay@4d2.org>
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Link: https://lore.kernel.org/r/20250811-k1-clk-i2s-v5-2-ebadd06e1e91@linux.spacemit.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>
|
|
Return 0 instead of -EINVAL if function ccu_pll_recalc_rate() fails to
get correct rate entry. Follow .recalc_rate callback documentation
as mentioned in include/linux/clk-provider.h for error return value.
Signed-off-by: Akhilesh Patil <akhilesh@ee.iitb.ac.in>
Fixes: 1b72c59db0add ("clk: spacemit: Add clock support for SpacemiT K1 SoC")
Reviewed-by: Haylen Chu <heylenay@4d2.org>
Reviewed-by: Alex Elder <elder@riscstar.com>
Link: https://lore.kernel.org/r/aIBzVClNQOBrjIFG@bhairav-test.ee.iitb.ac.in
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
RISC-V SpacemiT Reset for 6.17
- Add reset driver support for K1 SoC
* tag 'spacemit-reset-for-6.17-1':
reset: spacemit: add support for SpacemiT CCU resets
clk: spacemit: define three reset-only CCUs
clk: spacemit: set up reset auxiliary devices
soc: spacemit: create a header for clock/reset registers
dt-bindings: soc: spacemit: define spacemit,k1-ccu resets
Signed-off-by: Yixun Lan <dlan@gentoo.org>
|
|
The pll1_d8 clock is enabled by the boot loader, and is ultimately a
parent for numerous clocks, including those used by APB and AXI buses.
Guodong Xu discovered that this clock got disabled while responding to
getting -EPROBE_DEFER when requesting a reset controller.
The needed clock (CLK_DMA, along with its parents) had already been
enabled. To respond to the probe deferral return, the CLK_DMA clock
was disabled, and this led to parent clocks also reducing their enable
count. When the enable count for pll1_d8 was decremented it became 0,
which caused it to be disabled. This led to a system hang.
Marking that clock critical resolves this by preventing it from being
disabled.
Define a new macro CCU_FACTOR_GATE_DEFINE() to allow clock flags to
be supplied for a CCU_FACTOR_GATE clock.
Fixes: 1b72c59db0add ("clk: spacemit: Add clock support for SpacemiT K1 SoC")
Signed-off-by: Alex Elder <elder@riscstar.com>
Tested-by: Guodong Xu <guodong@riscstar.com>
Reviewed-by: Haylen Chu <heylenay@4d2.org>
Link: https://lore.kernel.org/r/20250612224856.1105924-1-elder@riscstar.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>
|
|
Three CCUs on the SpacemiT K1 SoC implement only resets, not clocks.
Define the CCU data for these resets so their auxiliary devices get
created.
Signed-off-by: Alex Elder <elder@riscstar.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20250702113709.291748-5-elder@riscstar.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>
|
|
Add a new reset_name field to the spacemit_ccu_data structure. If it is
non-null, the CCU implements a reset controller, and the name will be
used in the name for the auxiliary device that implements it.
Define a new type to hold an auxiliary device as well as the regmap
pointer that will be needed by CCU reset controllers. Set up code to
initialize and add an auxiliary device for any CCU that implements reset
functionality.
Make it optional for a CCU to implement a clock controller. This
doesn't apply to any of the existing CCUs but will for some new ones
that will be added soon.
Signed-off-by: Alex Elder <elder@riscstar.com>
Reviewed-by: Haylen Chu <heylenay@4d2.org>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20250702113709.291748-4-elder@riscstar.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>
|
|
Move the definitions of register offsets and fields used by the SpacemiT
K1 SoC CCUs into a separate header file, so that they can be shared by
the reset driver that will be found under drivers/reset.
Signed-off-by: Alex Elder <elder@riscstar.com>
Reviewed-by: Haylen Chu <heylenay@4d2.org>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20250702113709.291748-3-elder@riscstar.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>
|
|
The control register for TWSI8 clocks, APBC_TWSI8_CLK_RST, contains mux
selection bits, reset assertion bit and enable bits for function and bus
clocks. It has a quirk that reading always results in zero.
As a workaround, let's hardcode the mux value as zero to select
pll1_d78_31p5 as parent and treat twsi8_clk as a gate, whose enable mask
is combined from the real bus and function clocks to avoid the
write-only register being shared between two clk_hws, in which case
updates of one clk_hw zero the other's bits.
With a 1:1 factor serving as placeholder for the bus clock, the I2C-8
controller could be brought up, which is essential for boards attaching
power-management chips to it.
Signed-off-by: Haylen Chu <heylenay@4d2.org>
Reviewed-by: Alex Elder <elder@riscstar.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20250416135406.16284-5-heylenay@4d2.org
Signed-off-by: Yixun Lan <dlan@gentoo.org>
|
|
The clock tree of K1 SoC contains three main types of clock hardware
(PLL/DDN/MIX) and has control registers split into several multifunction
devices: APBS (PLLs), MPMU, APBC and APMU.
All register operations are done through regmap to ensure atomicity
between concurrent operations of clock driver and reset,
power-domain driver that will be introduced in the future.
Signed-off-by: Haylen Chu <heylenay@4d2.org>
Reviewed-by: Alex Elder <elder@riscstar.com>
Reviewed-by: Inochi Amaoto <inochiama@outlook.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20250416135406.16284-4-heylenay@4d2.org
Signed-off-by: Yixun Lan <dlan@gentoo.org>
|
