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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/aspeed,dwc3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Aspeed SuperSpeed DWC3 USB SoC controller
maintainers:
- Ryan Chen <ryan_chen@aspeedtech.com>
description:
The common content of the node is defined in snps,dwc3.yaml.
select:
properties:
compatible:
contains:
const: aspeed,ast2700-xhci
required:
- compatible
properties:
compatible:
items:
- const: aspeed,ast2700-xhci
- const: snps,dwc3
interrupts:
maxItems: 1
clocks:
items:
- description: Controller bus early clock
- description: PHY reference clock
- description: Controller suspend clock
clock-names:
items:
- const: bus_early
- const: ref
- const: suspend
resets:
maxItems: 1
phys:
maxItems: 1
phy-names:
const: usb3-phy
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- phys
- phy-names
allOf:
- $ref: snps,dwc3.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/aspeed,ast2700-scu.h>
#include <dt-bindings/reset/aspeed,ast2700-scu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
bus {
#address-cells = <2>;
#size-cells = <2>;
usb@12030000 {
compatible = "aspeed,ast2700-xhci", "snps,dwc3";
reg = <0x0 0x12030000 0x0 0x10000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon0 SCU0_CLK_GATE_PORTAUSB2CLK>,
<&syscon0 SCU0_CLK_U2PHY_REFCLK>,
<&syscon0 SCU0_CLK_U2PHY_CLK12M>;
clock-names = "bus_early", "ref", "suspend";
resets = <&syscon0 SCU0_RESET_PORTA_XHCI>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb3axh_default &pinctrl_usb2axh_default>;
phys = <&uphy3a>;
phy-names = "usb3-phy";
dr_mode = "host";
};
};
|
