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| author | Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> | 2026-06-18 13:37:13 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2026-06-28 11:08:13 +0530 |
| commit | a2077d44cc5743b2fae084dd3cac9225e81bc2fb (patch) | |
| tree | fbc23e1e54586e83cf34f9445f4493227fd9f439 | |
| parent | a8be5e9478be08f09a720f7013ec30d6e2bd9fcc (diff) | |
| download | opensbi-a2077d44cc5743b2fae084dd3cac9225e81bc2fb.tar.gz opensbi-a2077d44cc5743b2fae084dd3cac9225e81bc2fb.zip | |
platform: generic: mips eyeq7h: fix boot with JTAG
When JTAG is connected, internal logic leads to the bit
MIPS_CTL0_DBG_RST_DASRT (for the debug unit) stay high and
this prevents normal cluster power-up.
Force proper power-on reset value prior to power-up sequence.
Hold this value for about 10 usec
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
Link: https://lore.kernel.org/r/20260618103713.2588984-1-vladimir.kondratiev@mobileye.com
Signed-off-by: Anup Patel <anup@brainfault.org>
| -rw-r--r-- | platform/generic/mips/eyeq7h.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/platform/generic/mips/eyeq7h.c b/platform/generic/mips/eyeq7h.c index 242cbb3c..30af096c 100644 --- a/platform/generic/mips/eyeq7h.c +++ b/platform/generic/mips/eyeq7h.c @@ -73,7 +73,13 @@ static void eyeq7h_powerup_olb(u32 hartid) /* Get the MIPS_CM_CTL0 address */ cmd = (volatile void *)(MIPS_OLB_ADDR[cl] + MIPS_CM_CTL0); - temp = readl(cmd); + /* set reset value. Value may be wrong after JTAG debug session */ + temp = MIPS_CTL0_CACHE_HW_INIT_INHIBIT | + INSERT_FIELD(0, MIPS_CTL0_DBU_COLD_PWR_UP, 2) | + MIPS_CTL0_DBU_PWR_UP | MIPS_CTL0_CM_PWR_UP; + writel(temp, cmd); + wmb(); + sbi_timer_udelay(10); /* Enable HW cache init */ temp = temp & ~MIPS_CTL0_CACHE_HW_INIT_INHIBIT; /* deassert reset */ |