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| author | Chao-ying Fu <icebergfu@gmail.com> | 2025-02-25 17:47:27 -0800 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2025-03-28 18:52:05 +0530 |
| commit | 995f226f3f335864d2fca6254af32fa7ab0162e6 (patch) | |
| tree | 9d5ce99d29cc14595f9ea5b7d21c46c0f5199730 /docs | |
| parent | 8fe835303c4c7d134f07002c234ec5ec637953ca (diff) | |
| download | opensbi-995f226f3f335864d2fca6254af32fa7ab0162e6.tar.gz opensbi-995f226f3f335864d2fca6254af32fa7ab0162e6.zip | |
lib: Emit lr and sc instructions based on -march flags
When -march=rv64im_zalrsc_zicsr is used, provide atomic operations
and locks using lr and sc instructions only.
Signed-off-by: Chao-ying Fu <cfu@mips.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20250226014727.19710-1-cfu@mips.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/platform_requirements.md | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/docs/platform_requirements.md b/docs/platform_requirements.md index a843febf..dfda4f48 100644 --- a/docs/platform_requirements.md +++ b/docs/platform_requirements.md @@ -19,6 +19,10 @@ Base Platform Requirements The base RISC-V platform requirements for OpenSBI are as follows: 1. At least rv32ima_zicsr or rv64ima_zicsr required on all HARTs + + * Users may restrict the usage of atomic instructions to lr/sc + via rv32im_zalrsc_zicsr or rv64im_zalrsc_zicsr if preferred + 2. At least one HART should have S-mode support because: * SBI calls are meant for RISC-V S-mode (Supervisor mode) |