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authorVladimir Kondratiev <vladimir.kondratiev@mobileye.com>2026-02-23 16:54:45 +0200
committerAnup Patel <anup@brainfault.org>2026-02-25 18:49:03 +0530
commit52ac3de50c164c1d3cf4099e949cd818e1145440 (patch)
treeee0c34ae732b58f2171cdac2412e15781c34214e /platform
parent6545b78bcd82dabf07a14c65fce32e6fcd85394b (diff)
downloadopensbi-52ac3de50c164c1d3cf4099e949cd818e1145440.tar.gz
opensbi-52ac3de50c164c1d3cf4099e949cd818e1145440.zip
platform: generic: mips p8700: faster core boot
When powering up cores, wait for power up to complete using tight loop. This saves 10ms delay observed for every core Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-6-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'platform')
-rw-r--r--platform/generic/mips/p8700.c53
1 files changed, 30 insertions, 23 deletions
diff --git a/platform/generic/mips/p8700.c b/platform/generic/mips/p8700.c
index 48fce1d8..33b80dc1 100644
--- a/platform/generic/mips/p8700.c
+++ b/platform/generic/mips/p8700.c
@@ -61,10 +61,24 @@ static void power_up_other_cluster(u32 hartid)
sbi_printf("ERROR: Fail to power up cluster %u\n", cl);
}
+
+struct mips_boot_params {
+ u32 hartid;
+ bool local_p;
+ u32 target_state;
+};
+
+static bool mips_hart_reached_state(void *arg)
+{
+ struct mips_boot_params *p = arg;
+ u32 stat = read_cpc_co_stat_conf(p->hartid, p->local_p);
+
+ stat = EXT(stat, CPC_Cx_STAT_CONF_SEQ_STATE);
+ return stat == p->target_state;
+}
+
static int mips_hart_start(u32 hartid, ulong saddr)
{
- unsigned int stat;
- unsigned int timeout;
bool local_p = (cpu_cluster(current_hartid()) == cpu_cluster(hartid));
/* Hart 0 is the boot hart, and we don't use the CPC cmd to start. */
@@ -75,6 +89,14 @@ static int mips_hart_start(u32 hartid, ulong saddr)
write_gcr_co_reset_base(hartid, (unsigned long)mips_warm_boot, local_p);
if (cpu_hart(hartid) == 0) {
+ unsigned int const timeout_ms = 10;
+ bool booted;
+ struct mips_boot_params p = {
+ .hartid = hartid,
+ .local_p = local_p,
+ .target_state = CPC_Cx_STAT_CONF_SEQ_STATE_U6,
+ };
+
/* Ensure its coherency is disabled */
write_gcr_co_coherence(hartid, 0, local_p);
@@ -84,28 +106,13 @@ static int mips_hart_start(u32 hartid, ulong saddr)
/* Reset cluster cl core co hart 0 */
write_cpc_co_cmd(hartid, CPC_Cx_CMD_RESET, local_p);
- timeout = 100;
- while (true) {
- stat = read_cpc_co_stat_conf(hartid, local_p);
- stat = EXT(stat, CPC_Cx_STAT_CONF_SEQ_STATE);
- if (stat == CPC_Cx_STAT_CONF_SEQ_STATE_U6)
- break;
-
- /* Delay a little while before we start warning */
- if (timeout) {
- sbi_timer_mdelay(10);
- timeout--;
- }
- else {
- sbi_printf("Waiting for cluster %u core %u hart %u to start... STAT_CONF=0x%x\n",
- cpu_cluster(hartid),
- cpu_core(hartid), cpu_hart(hartid),
- stat);
- break;
- }
+ booted = sbi_timer_waitms_until(mips_hart_reached_state, &p, timeout_ms);
+ if (!booted) {
+ sbi_printf("ERROR: failed to boot hart 0x%x in %d ms\n",
+ hartid, timeout_ms);
+ return -SBI_ETIMEDOUT;
}
- }
- else {
+ } else {
write_cpc_co_vp_run(hartid, 1 << cpu_hart(hartid), local_p);
}