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| author | Nick Hu <nick.hu@sifive.com> | 2025-11-14 11:22:46 +0800 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2025-12-08 10:01:05 +0530 |
| commit | ec51e91eaa4e55e6babe0b37387645e75f7ded61 (patch) | |
| tree | e02edce7ec8f599df4beed17b943a748cdf346ac /platform | |
| parent | 35aece218a1da347e7c276a18c4ccdbda32ebec9 (diff) | |
| download | opensbi-ec51e91eaa4e55e6babe0b37387645e75f7ded61.tar.gz opensbi-ec51e91eaa4e55e6babe0b37387645e75f7ded61.zip | |
lib: utils/cache: Add SiFive PL2 controller
SiFive Private L2(PL2) cache is a private cache owned by each hart. Add
this driver to support private cache flush operations via the MMIO
registers.
Co-developed-by: Eric Lin <eric.lin@sifive.com>
Signed-off-by: Eric Lin <eric.lin@sifive.com>
Co-developed-by: Zong Li <zong.li@sifive.com>
Signed-off-by: Zong Li <zong.li@sifive.com>
Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Co-developed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Nick Hu <nick.hu@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-2-8423a721924c@sifive.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'platform')
| -rw-r--r-- | platform/generic/configs/defconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig index 3896b0e0..1bb14c78 100644 --- a/platform/generic/configs/defconfig +++ b/platform/generic/configs/defconfig @@ -13,6 +13,7 @@ CONFIG_PLATFORM_MIPS_P8700=y CONFIG_PLATFORM_SPACEMIT_K1=y CONFIG_FDT_CACHE=y CONFIG_FDT_CACHE_SIFIVE_CCACHE=y +CONFIG_FDT_CACHE_SIFIVE_PL2=y CONFIG_FDT_CPPC=y CONFIG_FDT_CPPC_RPMI=y CONFIG_FDT_GPIO=y |