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5 dayslib: utils/mpxy: Add RPMI MPXY driver for logging service groupHEADmasterSubrahmanya Lingappa
Add RPMI MPXY proxy driver for LOGGING service group so that S-mode can leverage LOGGING service group implemented by the platform microcontroller. Reviewed-by: Rahul Pathak <rahul.pathak@oss.qualcomm.com> Signed-off-by: Subrahmanya Lingappa <subrahmanya.lingappa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260619103424.990954-1-subrahmanya.lingappa@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
7 daysinclude: Bump-up version to 1.9v1.9Anup Patel
Update the OpenSBI version to 1.9 as part of release preparation. Signed-off-by: Anup Patel <anup@brainfault.org>
2026-06-17lib: sbi: Rework misaligned vector load/storeBo Gan
Fix the following issues with misaligned vector load/store: a. Stack overflow: the mask[VLEN_MAX / 8] variable consumes 8K stack space, given VLEN_MAX=65536, overflowing the default-sized stack. There's no need to fetch the whole mask in one go, instead, make it on-demand. Use a 128-byte mask as local buffer to hold the sliding window of mask. For rvv load, this is allowed -- from the spec: "The destination vector register group for a masked vector instruction cannot overlap the source mask register (v0), unless the destination vector register is being written with a mask value (e.g., compares) or the scalar result of a reduction" We don't need to worry about the mask getting overwritten. b. Maintain the value of vstart upon abort (uptrap) to avoid duplicate work. After fault resolution, the instruction can restart from the faulting vstart. For Fault-Only-First loads, reset vstart to 0, as previously done so, to conform to spec. c. Explicitly set VS dirty in VSSTATUS with SET_VS_DIRTY() if faulting from V=1, and if any vector register, including vstart/vl/vtype, gets changed in the handler. It can add 1 unnecessary op to set VS dirty in M/SSTATUS (not VSSTATUS), where the HW already did, but for code simplicity, do it anyway. The overhead should be negligible. Signed-off-by: Bo Gan <ganboing@gmail.com> Tested-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260609060024.706-5-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-06-17lib: sbi: Add variable-length unprivilege access functionsBo Gan
sbi_load/store_loop read/write variable-length buffer unprivileged. Both function use the widest aligned 8/4/2/1 byte load/stores in each loop to reduce the total number of iterations. Also switch the scalar/vector misaligned handlers to make use of such functions to simplify code. Miscellaneous: remove the unnecessary [taddr] in inline assembly Signed-off-by: Bo Gan <ganboing@gmail.com> Tested-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260609060024.706-4-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-06-17lib: sbi: Rework and split sbi_misaligned(_v)_tinst_fixupBo Gan
The load/store address offset between the uptrap and the orig_trap can be derived by orig_trap->tval - uptrap->tval, thus refactor the function prototype for simplicity. For vector load, sbi_misaligned_v_tinst_fixup is introduced. There's no transformed instruction for vector load/store, so null out tinst if the fault is not a guest-page fault. Signed-off-by: Bo Gan <ganboing@gmail.com> Tested-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260609060024.706-3-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-06-16lib: sbi: Make per-HART stack size configurable via KconfigOriol Catalan
The per-HART stack size for exception/interrupt handling is currently hardcoded to 8192 bytes in SBI_PLATFORM_DEFAULT_HART_STACK_SIZE. This may not be sufficient for platforms with deeper call stacks (e.g. those enabling additional SBI extensions) or may be wasteful for minimal platforms. Introduce a HART_STACK_SIZE Kconfig option in lib/sbi/Kconfig with a valid range of 8192 to 1048576 bytes and a default of 8192 bytes to preserve existing behavior. The SBI_PLATFORM_DEFAULT_HART_STACK_SIZE macro now resolves to CONFIG_HART_STACK_SIZE, allowing all platforms to benefit from a single configuration knob without any source changes. Signed-off-by: Oriol Catalan <oriol.catalan@openchip.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/VI0P192MB3062735A6194BB6DA72083499E002@VI0P192MB3062.EURP192.PROD.OUTLOOK.COM Signed-off-by: Anup Patel <anup@brainfault.org>
2026-06-16lib: sbi: Do not override emulator callback for vector load/storeBo Gan
It's wrong to override the emulator callback in sbi_trap_emulate_load/ store. The function must respect the callback function passed in the parameter. Hence, let the misaligned emulator callback decide when to use sbi_misaligned_v_ld/st_emulator. To clean up things, also make the following changes: - Add the `insn` parameter to the callback. The trapping insn has been fetched by the caller already, whether transformed or directly loaded, thus saving the trouble in the callback. Note that you must not rely on the length of the `insn`, as it can be a transformed one from tinst - Also the `tcntx` is added, providing the callback with register values to handle vector insn or other customized insns. - Clarify that the read/write length (rlen/wlen) can be 0, in which case it could be a vector load/store or some customized instruction. The callback is responsible to handle it accordingly. Also fixed issues in the sbi_misaligned_v_ld/st_emulator: a. Redirect the trap when OPENSBI_CC_SUPPORT_VECTOR is not available. b. Ensure the return code is >0 when no faults are redirected. Fixes: c2acc5e5b0d8 ("lib: sbi_misaligned_ldst: Add handling of vector load/store") Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Tested-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com> Link: https://lore.kernel.org/r/20260605113214.242-6-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-06-16include: sbi: set FS dirty in vsstatus when V=1Bo Gan
According to Privileged ISA 19.2.11: Modifying the floating-point state when V=1 causes both fields (vsstatus.FS and the HS-level sstatus.FS) to be set to 3 (Dirty) Fixes: 130e65dd9d44 ("lib: sbi: Implement SET_FS_DIRTY() to make sure the mstatus FS dirty is set") Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Tested-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com> Link: https://lore.kernel.org/r/20260605113214.242-5-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-06-16include: sbi: Add GET_RDS_NUM/SET(_FP32/_FP64)_RDS macrosBo Gan
These macros can be used to decode rd' and set rd' in RVC instructions Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Tested-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com> Link: https://lore.kernel.org/r/20260605113214.242-4-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-06-16include: sbi: Add sbi_regs_prev_xlenBo Gan
sbi_regs_prev_xlen reports the xlen of previous mode by decoding from multiple CSRs including mstatus/hstatus/vsstatus Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Tested-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com> Link: https://lore.kernel.org/r/20260605113214.242-3-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-06-16include: sbi: Add more mstatus and instruction encodingBo Gan
- Add MXL encoding for calculating XLEN. - Add instruction encoding for c.lbu/c.sb, and imm encoding for multiple RVC insn. Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Tested-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com> Link: https://lore.kernel.org/r/20260605113214.242-2-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-06-15include: utils/hsm: Add __noreturn attribute for sifive_ceaseBo Gan
Decorate the sifive_cease to allow more compiler optimizations Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260605075708.96-2-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-06-12platform: generic: Optimize extensions_init() to parse ISA extensions onceAnup Patel
Instead of parsing ISA extensions separately for each hart in the generic_extensions_init() function, it is better to parse ISA extensions for all available harts in the cold boot path. Also, this allows us to remove fdt_isa_bitmap from scratch space and directly initialize "extensions" in struct sbi_hart_features for each hart. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260521082625.1520870-3-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-06-12lib: sbi: add UBSan supportMarcos Oduardo
UBSan (Undefined Behavior Sanitizer) is a tool implemented using compiler instrumentation at runtime that allows checking for statements whose output is not deterministic or defined by the C standard. Compiling and running OpenSBI with UBSan instrumentation will print a message in the console if any sentence performs such an action. Support involves two main components: 1. The UBSan implementation hooks (derived from NetBSD), used by the compiler to handle the check output. 2. A test suite integrated with the SBI unit test framework to verify correct operation at runtime. Usage: make UBSAN=y PLATFORM=generic ... The test suite is built when both UBSAN=y and CONFIG_SBIUNIT=y are enabled. When UBSan is enabled, FW_PAYLOAD_OFFSET may need to be increased due to the size increase added by the instrumentation. A value of 0x400000 has been tested. UBSan adds runtime overhead and is intended for development builds only, not for production. Note: This patch marks __stack_chk_guard in sbi_init.c as a weak symbol to prevent multiple definition errors at compile time with UBSan instrumentation enabled. This resolves the conflict between the .globl definitions in sbi_init.c and test_head.S. Signed-off-by: Marcos Oduardo <marcos.oduardo@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260515163321.2038366-1-marcos.oduardo@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-06-10include: sbi: Add SBI MPXY notification related definesDavid E. Garcia Porras
The SBI MPXY notification header related offsets are missing from the sbi_ecall_interface.h hence add these defines. Signed-off-by: David E. Garcia Porras <david.garcia@aheadcomputing.com> Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260608125257.3220114-5-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-06-10include: mailbox: Update RPMI notification structs and add performance eventsDavid E. Garcia Porras
Add rpmi_event_notification_state enum with disable, enable, and return current state IDs. Also, add req_state field to rpmi_enable_notification_req and current_state field to rpmi_enable_notification_resp for RPMI specification compliance. Add notification event ID enum and data structures for RPMI Performance service group events: power change, limit change, and level change. Signed-off-by: David E. Garcia Porras <david.garcia@aheadcomputing.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260608125257.3220114-4-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-06-10lib: sbi_irqchip: Allow irqchip drivers advertise capabilitiesAnup Patel
Extend struct sbi_irqchip_device to allow irqchip drivers advertise interrupt controller capabilities (such as wired interrupt, MSIs, etc). This further allows other parts of OpenSBI to lookup irqchip devices based on capabilities. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260608125257.3220114-2-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-06-10lib: sbi: Move hart PMP functions to sbi_hart_pmp.cNicholas Piggin
The sbi_hart_pmp.c looks like a good place for the hart PMP CSR access functions. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260430045528.420437-9-npiggin@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-06-10lib: sbi: Add hart_ prefix to PMP functionsNicholas Piggin
PMP functions that deal with hart PMP CSRs are given a sbi_hart_ prefix, to distinguish from RISC-V PMP encoding functions. The is_pmp_entry_mapped() function is changed a little more, to align with other PMP conventions, and made to return a bool to make it more obvious that it returns a bool and not an SBI_ return code. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260430045528.420437-8-npiggin@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-06-10lib: sbi: Add sbi_pmp_is_enabled() helperNicholas Piggin
Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260430045528.420437-7-npiggin@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-06-10lib: sbi: Move RISC-V PMP encoding functions to sbi_pmp.cNicholas Piggin
Create a new file for handling the RISC-V PMP format and the new pmp_t type, as opposed to hart PMP CSR specific access. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260430045528.420437-4-npiggin@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-06-07include: mailbox: rpmi_msgprot: Add RPMI performance domain flag definesDavid E. Garcia Porras
Add bit-field defines for the RPMI performance domain attributes flags and fast-channel attributes flags as specified in the RPMI specification. These are needed by platform implementations that provide RPMI performance services (e.g. DVFS controllers). Also add the missing db_write_value field to rpmi_perf_get_fast_chn_attr_resp to match the RPMI spec layout. Signed-off-by: David E. Garcia Porras <david.garcia@aheadcomputing.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260328054347.3706029-5-david.garcia@aheadcomputing.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-05-18lib: sbi: domain FP/Vector context support for context switchDave Patel
This patch adds proper support for per-domain floating-point (FP) and vector (V) contexts in the domain context switch logic. Each domain now maintains its own FP and vector state, which is saved and restored during domain switches. Conditionalize FP and Vector save/restore based on extensions, unconditional save and restore of floating-point (FP) and Vector registers fails on generic platform firmware. This firmware must run on multiple platforms that may lack these extensions. Address this by conditionally executing FP save/restore only if the underlying hart supports the F or D extensions. Similarly, perform Vector save/restore only if the hart supports the Vector extension. This improves support for multi-domain systems with FP and Vector extensions, and prevents corruption of FP/Vector state during domain switches. Signed-off-by: Dave Patel <dave.patel@riscstar.com> Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260518083023.997323-4-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-05-18lib: sbi: Add floating-point context save/restore support.Dave Patel
Add support for saving and restoring RISC-V floating-point (F/D) extension state in OpenSBI. This introduces a floating-point context structure and helper routines to perform full context save and restore. The floating-point context includes storage for all 32 FPi registers (f0–f31) along with the fcsr control and status register. The register state is saved and restored using double-precision load/store instructions (fsd/fld), and single-precision load/store instructions (fsw/flw) on an RV64 system with F and D-extension support. The implementation follows an eager context switching model where the entire FP state is saved and restored on every context switch. This avoids the need for trap-based lazy management and keeps the design simple and deterministic. Signed-off-by: Dave Patel <dave.patel@riscstar.com> Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260518083023.997323-3-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-05-18lib: sbi: Add RISC-V vector context save/restore supportDave Patel
Eager context switch: Add support for saving and restoring RISC-V vector extension state in OpenSBI. This introduces a per-hart vector context structure and helper routines to perform full context save and restore. The vector context includes vcsr CSRs along with storage for all 32 vector registers. The register state is saved and restored using byte-wise vector load/store instructions (vs8r/vl8r). The implementation follows an eager context switching model where the entire vector state is saved and restored on every context switch. This provides a simple and deterministic mechanism without requiring lazy trap-based management. Signed-off-by: Dave Patel <dave.patel@riscstar.com> Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260518083023.997323-2-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-05-12lib: sbi_irqchip: Add support for registering MSI handlersAnup Patel
Some of the drivers (such as APLIC) require capability to registers MSI handlers from the parent interrupt controller (such as IMSIC) so add sbi_irqchip_register_msi_handler() for this purpose. Link: https://lore.kernel.org/r/20260423052339.356900-7-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-05-12lib: sbi_irqchip: Allow setting hardware interrupt affinityAnup Patel
The irqchip drivers can provide mechanism to set interrupt affinity so add hwirq_set_affinity() callback for irqchip drivers and use it to implement sbi_irqchip_set_affinity() which can be used by other drivers. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260423052339.356900-6-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-05-12lib: sbi_irqchip: Allow marking hardware interrupts as reservedAnup Patel
Some of the hardware interrupts may be special so allow irqchip drivers to make these hardware interrupts as reserved. Introduce sbi_irqchip_register_reserved() for this purpose. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260423052339.356900-5-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-05-12lib: sbi_irqchip: Allow interrupt client to specify line sensingAnup Patel
The interrupt client should be allowed to specify the line sensing type of the hwirqs for which it is registering handler. To support this, add hwirq_flags parameter to hwirq_setup() callback provided by the irqchip driver. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260423052339.356900-4-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-05-09lib: sbi_timer: Introduce sbi_timer_compute_delta() and friendsAnup Patel
The users of timer event have to compute next_event (aka timer value in the future) based on desired units and unit frequency. Introduce sbi_timer_compute_delta() and friends to simplify computing next_event for timer event users. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Link: https://lore.kernel.org/r/20260425104048.2335262-5-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-05-09lib: sbi_timer: Add support for timer eventsAnup Patel
Currently, the sbi_timer only supports timer events configured via SBI calls. Introduce struct sbi_timer_event and related functions to allow configuring timer events from any part of OpenSBI. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Link: https://lore.kernel.org/r/20260425104048.2335262-4-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-05-09include: sbi: Add sbi_scratch_hartindex() macroAnup Patel
Add helper macro to extract hart index from scratch pointer. This can be used to check whether scratch pointer belongs to a particular hart or not. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Link: https://lore.kernel.org/r/20260425104048.2335262-2-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-05-09lib: sbi: hart: Detect and enable Smrnmi before trap-based feature detectionEvgeny Voevodin
The location of the RNMI/E trap vectors in the Smrnmi extension is implementation-defined, so platforms with vendor-specific NMI vector mechanisms must install the firmware's NMI entry points themselves. Add an smrnmi_handlers_init() callback to sbi_platform_operations that receives the firmware entry points and lets platform code install them at the hardware-specific vector locations. Two pointers are passed: - _trap_rnmi_handler: the dedicated RNMI entry point that saves context using the Smrnmi MN* CSRs and returns via mnret. - _trap_handler: the regular M-mode trap entry since RNME is taken as a regular M-mode trap with NMIE=0. When Smrnmi is present, install the platform's NMI vectors via the new callback, initialize MNSCRATCH with the per-hart scratch pointer, and set MNSTATUS.NMIE. Smrnmi-enabled platforms must register smrnmi_handlers_init; if the extension is detected but no callback is registered, sbi_panic() is called since enabling NMIs without handlers in place would route subsequent traps into nowhere. Signed-off-by: Evgeny Voevodin <evvoevod@tenstorrent.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/88b1470e1e3348d454b4b995a11a85c01914f7af.1778176768.git.evvoevod@tenstorrent.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-05-09firmware: Add RNMI handler infrastructureEvgeny Voevodin
Implement basic Resumable NMI (RNMI) handler support for the RISC-V Smrnmi extension. The new _trap_rnmi_handler assembly entry point saves context using the Smrnmi MN* CSRs (MNSCRATCH, MNEPC, MNSTATUS, MNCAUSE) and returns via mnret. It dispatches to sbi_trap_rnmi_handler(), which optionally calls a platform-specific ops->rnmi_handler callback for actual NMI processing. If no platform handler is registered or it fails, the event is reported as an unhandled NMI. The RNMI handler reuses the generic trap context structure but stores MN* CSR values (MNEPC, MNSTATUS, MNCAUSE) into the corresponding generic fields (mepc, mstatus, cause) for compatibility with existing trap infrastructure. Signed-off-by: Evgeny Voevodin <evvoevod@tenstorrent.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/050ae6d2762ba8d5b9dfb3cc1960a23aa3d6c549.1778176768.git.evvoevod@tenstorrent.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-05-09lib: sbi: Add Smrnmi extension macros for registers and bitsEvgeny Voevodin
Add CSR definitions (MNSCRATCH, MNSTATUS, MNEPC, MNCAUSE) and bit definitions (MNSTATUS_NMIE, MNSTATUS_MNPV, MNSTATUS_MNPP). Also add SBI_HART_EXT_SMRNMI to the hart extension enumeration. Signed-off-by: Evgeny Voevodin <evvoevod@tenstorrent.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/1c6feb6d359b9827b3c2ad8f4f0e0a4dfd1de911.1778176768.git.evvoevod@tenstorrent.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-05-09include: sbi_scratch: Add tmp1 scratch space for RNMI context savingEvgeny Voevodin
RNMI handlers use MNSCRATCH instead of MSCRATCH and need separate scratch space from regular trap handling. Add tmp1 for RNMI context while tmp0 remains for regular traps. Signed-off-by: Evgeny Voevodin <evvoevod@tenstorrent.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/0a5d241fa1db03e71a3f56be24708cbbc8037e28.1778176768.git.evvoevod@tenstorrent.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-04-08include: sbi_bitmap: add bitmap_empty() functionYu-Chien Peter Lin
Add bitmap_empty() to check if bitmap has no bits set. Unlike bitmap_weight() which calls sbi_popcount() on every word, bitmap_empty() uses simple non-zero comparisons with early exit. Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260311125116.1401002-1-peter.lin@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-04-06lib: utils: Add MPXY client driver for RPMI MM service groupRanbir Singh
Add necessary infra for implementing RPMI Management Mode service group on platform microcontroller. Co-authored-by: Sunil V L <sunilvl@oss.qualcomm.com> Signed-off-by: Ranbir Singh <ranbir.singh@oss.qualcomm.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260225061347.1396504-1-ranbir.singh@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: sbi_irqchip: Allow registering interrupt handlersAnup Patel
To handle external interrupts in M-mode, the sbi_irqchip framework must allow registering interrupt handlers from device drivers. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-9-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: sbi_irqchip: Associate 32-bit unique ID for each irqchip deviceAnup Patel
Allow locating irqchip device instance using a unique 32-bit ID. This 32-bit unique ID can be set by the irqchip driver at the time of adding irqchip device. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-8-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: utils/irqchip: Add unique_id to plic, aplic, and imsic dataAnup Patel
Add a 32-bit unique ID to plic, aplic, and imsic data which can be used to differentiate multiple irqchip devices. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-7-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: sbi_irqchip: Support irqchip device targetting subset of hartsAnup Patel
It is possible to have platform where an irqchip device targets a subset of harts and there are multiple irqchip devices to cover all harts. To support this scenario: 1) Add target_harts hartmask to struct sbi_irqchip_device which represents the set of harts targetted by the irqchip device 2) Call warm_init() and process_hwirqs() callbacks of an irqchip device on a hart only if irqchip device targets that particular hart Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-6-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: utils/irqchip: Add IDC to hartindex map in struct aplic_dataAnup Patel
A platform can have multiple APLICs in direct-mode targetting different subset of harts. Add APLIC ID to hartindex map in struct aplic_data to capture the set of harts targeted by a given APLIC in direct-mode. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-5-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: sbi_irqchip: Rename irq_handle() callback to process_hwirqs()Anup Patel
The irq_handle() callback of irqchip device is meant to process hardware interrupt of the irqchip hence rename it accordingly. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-3-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: sbi_irqchip: Use chip as variable name for irqchip deviceAnup Patel
The irqchip device represents an interrupt controller so use chip as variable name instead of dev. This will avoid confusion as the sbi_irqchip framework grows. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-2-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-09lib: sbi: Fix undefined behavior in signed shifts in sbi_hart.cMarcos Oduardo
UBSan detected undefined behavior in sbi_hart.c and sbi_fwft.c (in the case of sbi_fwft.c, the bug comes from a macro call defined at sbi_ecall_interface.h) caused by shifting a signed integer into the sign bit (1 << 31) This can be fixed by using the 1UL literal, ensuring defined arithmetic. Please let me know if there’s any other most suitable solution for this bug. Signed-off-by: Marcos Oduardo <marcos.oduardo@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223001202.284612-1-marcos.oduardo@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-09include: sbi: Fix illegal shift in sbi_domain.hMarcos Oduardo
In sbi_domain.h, when checking if a memory region is a subset of another, an undefined behavior arithmetic operation was caught when sanitizing with UBSan (shift exponent __riscv_xlen). This patch adds a check to handle the case where the region order is __riscv_xlen, avoiding the illegal shift and ensuring the operation remains defined. Please let me know if there’s any other most suitable solution for this bug. Signed-off-by: Marcos Oduardo <marcos.oduardo@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260222235219.276432-1-marcos.oduardo@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-21lib: sbi_pmu: Add FW counter index validation when reading high bits on RV64James Raphael Tiovalen
Currently, when we attempt to read the upper 32 bits of a firmware counter on RV64 or higher, we just set `sbiret.value` to 0 without validating the counter index. The SBI specification requires us to set `sbiret.error` to `SBI_ERR_INVALID_PARAM` if the counter index points to a hardware counter or an invalid counter. Add a validation check to ensure compliance with the specification on RV64 or higher. Fixes: 51951d9e9af8 ("lib: sbi_pmu: Implement sbi_pmu_counter_fw_read_hi") Signed-off-by: James Raphael Tiovalen <jamestiotio@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260125090643.190748-1-jamestiotio@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-20lib: utils/serial: Add support for Altera JTAG UARTIcenowy Zheng
Altera provides a JTAG UART core that provides virtual UART over JTAG and can coexist with their virtual JTAG. [1] This core has already been supported by Linux and the programming interface has always been stable. Add support for it to OpenSBI to ease JTAG prototype bringing up. The driver follows the device tree binding in mainline Linux. [2] [1] https://docs.altera.com/r/docs/683130/25.3/embedded-peripherals-ip-user-guide/jtag-uart-core [2] https://github.com/torvalds/linux/blob/v6.19-rc1/Documentation/devicetree/bindings/serial/altr%2Cjuart-1.0.yaml Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260104065506.70182-1-zhengxingda@iscas.ac.cn Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-20firmware: Initialize stack guard via ZkrXiang W
Try to initialize stack protection guard via the zkr extension. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260104051812.128496-1-wxjstz@126.com Signed-off-by: Anup Patel <anup@brainfault.org>
generated by cgit v1.2.3 (git 2.39.1) at 2026-07-07 02:31:44 +0000