diff options
| author | Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> | 2026-06-25 18:08:33 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2026-07-01 19:59:09 +1000 |
| commit | 5a3fd18f4f9b9c2a19c0800e88d7b38403e210ca (patch) | |
| tree | 93be0b07addf340b3a678f7a253ab57324dfdfb7 | |
| parent | 8a34849f5ba4f52a183c4ce21317ab9e832889a3 (diff) | |
| download | qemu-5a3fd18f4f9b9c2a19c0800e88d7b38403e210ca.tar.gz qemu-5a3fd18f4f9b9c2a19c0800e88d7b38403e210ca.zip | |
hw/riscv/riscv-iommu.c: make FCTL.BE read only 0
We do not support FCTL.BE equal to 1 hence do not allow this bit to be
set by software.
While we're at it: the riscv-iommu spec allows FCTL.GXL to be set freely
and we do not have hardcoded restrictions on it, so make it writable.
Fixes: 0c54acb824 ("hw/riscv: add RISC-V IOMMU base emulation")
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3576
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20260625210833.3294437-3-daniel.barboza@oss.qualcomm.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | hw/riscv/riscv-iommu.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index 30f16b999c..c9687e01a8 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -2609,9 +2609,11 @@ static void riscv_iommu_realize(DeviceState *dev, Error **errp) /* Set power-on register state */ stq_le_p(&s->regs[RISCV_IOMMU_REG_CAP], s->cap); + stq_le_p(&s->regs[RISCV_IOMMU_REG_FCTL], 0); stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_FCTL], - ~(RISCV_IOMMU_FCTL_BE | RISCV_IOMMU_FCTL_WSI)); + ~(RISCV_IOMMU_FCTL_GXL | RISCV_IOMMU_FCTL_WSI)); + stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_DDTP], ~(RISCV_IOMMU_DDTP_PPN | RISCV_IOMMU_DDTP_MODE)); stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_CQB], |