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| author | Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> | 2026-06-16 20:59:37 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2026-07-01 19:59:09 +1000 |
| commit | 5af6d1308b29a6dd426158706b2b70ef5cdc8d9d (patch) | |
| tree | 8e4f105783aaf22ffecf60253ea9e709a028c498 | |
| parent | 64d98e0797c821da99894517215539dea2ade7cd (diff) | |
| download | qemu-5af6d1308b29a6dd426158706b2b70ef5cdc8d9d.tar.gz qemu-5af6d1308b29a6dd426158706b2b70ef5cdc8d9d.zip | |
hw/riscv/sifive_u: add #address-cells in PLIC FDT
By Linux FDT docs in [1] the "address-cells" property is mandatory. Set
it to zero.
While we're at it let's also put this new value and the interrupt-cells
value in macros, like the 'virt' board is doing.
[1] https://www.kernel.org/doc/Documentation/devicetree/bindings/interrupt-controller/sifive%2Cplic-1.0.0.txt
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20260616235939.1358663-4-daniel.barboza@oss.qualcomm.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | hw/riscv/sifive_u.c | 5 | ||||
| -rw-r--r-- | include/hw/riscv/sifive_u.h | 2 |
2 files changed, 6 insertions, 1 deletions
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index b3468254f5..7dfc18d3ec 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -213,7 +213,10 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, nodename = g_strdup_printf("/soc/interrupt-controller@%lx", (long)memmap[SIFIVE_U_DEV_PLIC].base); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); + qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", + SIFIVE_U_PLIC_INT_CELLS); + qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", + SIFIVE_U_PLIC_ADDR_CELLS); qemu_fdt_setprop_string_array(fdt, nodename, "compatible", (char **)&plic_compat, ARRAY_SIZE(plic_compat)); qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index e4c9860d50..aed966a62d 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -156,6 +156,8 @@ enum { #define SIFIVE_U_MANAGEMENT_CPU_COUNT 1 #define SIFIVE_U_COMPUTE_CPU_COUNT 4 +#define SIFIVE_U_PLIC_ADDR_CELLS 0 +#define SIFIVE_U_PLIC_INT_CELLS 1 #define SIFIVE_U_PLIC_NUM_SOURCES 54 #define SIFIVE_U_PLIC_NUM_PRIORITIES 7 #define SIFIVE_U_PLIC_PRIORITY_BASE 0x00 |