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| author | Charlie Jenkins <thecharlesjenkins@gmail.com> | 2026-06-25 22:12:02 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2026-07-01 19:59:10 +1000 |
| commit | d6c782fdb9f0c98ccf8e54d70165420e58e3c767 (patch) | |
| tree | 521e6957c193a0e1ef82139b58c44026189096ce | |
| parent | 3cee183ff9a1a644fcc027ce2751276a5525b123 (diff) | |
| download | qemu-d6c782fdb9f0c98ccf8e54d70165420e58e3c767.tar.gz qemu-d6c782fdb9f0c98ccf8e54d70165420e58e3c767.zip | |
target/riscv: Report QEMU CPU archid as 42
When a non-vendor CPU is used, report the archid as 42 which has been
allocated for QEMU in the riscv isa manual [1]. This can help software
check if it is running in QEMU.
[1] https://github.com/riscv/riscv-isa-manual/blob/main/marchid.md
Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260625-marchid-v2-1-3821c351028b@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index bff3ed5de1..de94f5d57e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -47,6 +47,13 @@ static const char riscv_single_letter_exts[] = "IEMAFDQCBPVH"; const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV, RVC, RVS, RVU, RVH, RVG, RVB, 0}; +#define RISCV_CPU_MVENDORID 0 +#define RISCV_CPU_MIMPID 0 +/* + * marchid allocated for qemu: + * https://github.com/riscv/riscv-isa-manual/blob/main/marchid.md + */ +#define RISCV_CPU_MARCHID 42 /* * From vector_helper.c @@ -1204,6 +1211,10 @@ static void riscv_cpu_init(Object *obj) mcc->def->profile->enabled = true; } + cpu->cfg.mvendorid = RISCV_CPU_MVENDORID; + cpu->cfg.marchid = RISCV_CPU_MARCHID; + cpu->cfg.mimpid = RISCV_CPU_MIMPID; + env->misa_ext_mask = env->misa_ext = mcc->def->misa_ext; riscv_cpu_cfg_merge(&cpu->cfg, &mcc->def->cfg); |