Merge tag 'pull-riscv-to-apply-20260701' of https://github.com/alistair23/qemu into staging

RISC-V PR for 11.1

* Fix IMSIC CSR write and add tests
* Parametrise debug trigger number
* Add 'svbare' satp-mode
* Fix RINTC PLIC context ID for KVM
* Avoid abort when reading vtype before env->xl is set
* Skip reset for KVM irqchip
* Skip FP/Vector sync on KVM_PUT_RUNTIME_STATE
* More FDT cleanups (PLIC)
* Make FCTL.BE in IOMMU read only 0
* Check DC.TC reserved bits in IOMMU
* Apply UXL WARL handling to vsstatus
* Set cmd_ill IOFENCE.C if rsvp bits are set in IOMMU
* Set RISCV_IOMMU_FQ_HDR_PV appropriately
* Fix MSI MRIF IOMMU interrupt-pending offset
* Report QEMU CPU archid as 42
* Check PMP before updating PTE
* Add the Tenstorrent Atlantis machine

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* tag 'pull-riscv-to-apply-20260701' of https://github.com/alistair23/qemu: (39 commits)
  hw/riscv/riscv-iommu.c: always fault with SADE=0 and A=0
  hw/riscv/atlantis: Add some i2c peripherals
  hw/riscv/atlantis: Integrate i2c controllers
  hw/i2c: Add DesignWare I2C Controller
  tests/functional/riscv64: Add tt-atlantis tests
  hw/riscv/atlantis: Ensure OpenSBI has a non-zero next_addr
  hw/riscv: Add Tenstorrent Atlantis machine
  target/riscv: tt-ascalon: Enable Zkr extension
  hw/riscv/aia: Configure stride for the M-mode IMSIC
  hw/riscv/aia: Provide number of irq sources
  hw/riscv/virt: Move AIA initialisation to helper file
  hw/riscv/boot: Account for discontiguous memory when loading firmware
  hw/riscv/boot: Describe discontiguous memory in boot_info
  target/riscv: Check PMP before updating PTE
  target/riscv: Report QEMU CPU archid as 42
  hw/riscv/riscv-iommu.c: fix MSI MRIF interrupt-pending offset
  hw/riscv/riscv-iommu.c: set RISCV_IOMMU_FQ_HDR_PV appropriately
  hw/riscv/riscv-iommu: set cmd_ill IOFENCE.C rsvp bits are set
  target/riscv: Apply UXL WARL handling to vsstatus
  hw/riscv/riscv-iommu: check DC.TC reserved bits
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

2 files changed, 42 insertions, 0 deletions

diff --git a/docs/system/riscv/tt_atlantis.rst b/docs/system/riscv/tt_atlantis.rst
new file mode 100644
index 0000000000..1f2880d617
--- /dev/null
+++ b/docs/system/riscv/tt_atlantis.rst
@@ -0,0 +1,41 @@
+Tenstorrent Atlantis (``tt-atlantis``)
+======================================
+
+The Tenstorrent Atlantis platform is a collaboration between Tenstorrent
+and CoreLab Technology. It is based on the Atlantis SoC, which includes
+the Ascalon-X CPU and other IP from Tenstorrent and CoreLab Technology.
+
+The Tenstorrent Ascalon-X is a high performance 64-bit RVA23 compliant
+RISC-V CPU.
+
+tt-atlantis QEMU model features
+-------------------------------
+
+* 8-core Ascalon-X CPU Cluster
+* RISC-V compliant Advanced Interrupt Architecture
+* 16550A compatible UART
+
+Known limitations
+-----------------
+
+The QEMU tt-atlantis machine does not yet model every device on the
+real platform. Notably:
+
+* There is no PCI host bridge, so virtio-pci devices cannot be
+  attached. Boots that need block storage must use ``-initrd`` with
+  an initramfs.
+* The DesignWare UART is modelled with QEMU's ns16550-compatible
+  ``serial_mm`` device; DesignWare-specific registers beyond that
+  set return 0.
+
+Supported software
+------------------
+
+The Tenstorrent Ascalon CPUs avoid proprietary or non-standard
+extensions, so compatibility with existing software is generally
+good. The QEMU tt-atlantis machine works with upstream OpenSBI
+and Linux with default configurations.
+
+The development board hardware will require some implementation
+specific setup in firmware which is being developed and may
+become a requirement or option for the tt-atlantis machine.
diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
index 896f14e78b..2639866a3e 100644
--- a/docs/system/target-riscv.rst
+++ b/docs/system/target-riscv.rst
@@ -72,6 +72,7 @@ undocumented; you can get a complete list by running
    riscv/mips
    riscv/shakti-c
    riscv/sifive_u
+   riscv/tt_atlantis
    riscv/virt
    riscv/xiangshan-kunminghu