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-rw-r--r--docs/about/deprecated.rst9
-rw-r--r--docs/system/ppc/pseries.rst2
-rw-r--r--hw/pci-host/meson.build2
-rw-r--r--hw/pci-host/pnv_phb4.c6
-rw-r--r--hw/pci-host/pnv_phb4_pec.c58
-rw-r--r--hw/pci-host/pnv_phb5.c23
-rw-r--r--hw/pci-host/pnv_phb5_pec.c77
-rw-r--r--hw/ppc/pnv.c10
-rw-r--r--hw/ppc/ppc.c5
-rw-r--r--pc-bios/README2
-rw-r--r--pc-bios/slof.binbin994176 -> 997576 bytes
m---------roms/SLOF0
-rw-r--r--target/ppc/cpu.h1
-rw-r--r--target/ppc/cpu_init.c5
-rwxr-xr-xtests/functional/ppc64/test_powernv.py19
15 files changed, 139 insertions, 80 deletions
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index cf3e1a007c..169c5dfe4f 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -206,15 +206,6 @@ in the QEMU object model anymore. ``Sun-UltraSparc-IIIi+`` and
but for consistency these will get removed in a future release, too.
Use ``Sun-UltraSparc-IIIi-plus`` and ``Sun-UltraSparc-IV-plus`` instead.
-PPC 405 CPUs (since 10.0)
-'''''''''''''''''''''''''
-
-The PPC 405 CPU has no known users and the ``ref405ep`` machine was
-removed in QEMU 10.0. Since the IBM POWER [8-11] processors uses an
-embedded 405 for power management (OCC) and other internal tasks, it
-is theoretically possible to use QEMU to model them. Let's keep the
-CPU implementation for a while before removing all support.
-
Power8E and Power8NVL CPUs and corresponding Pnv chips (since 10.1)
'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst
index bbc51aa7fc..107091a37f 100644
--- a/docs/system/ppc/pseries.rst
+++ b/docs/system/ppc/pseries.rst
@@ -43,7 +43,7 @@ Firmware
The pSeries platform in QEMU comes with 2 firmwares:
-`SLOF <https://github.com/aik/SLOF>`_ (Slimline Open Firmware) is an
+`SLOF <https://gitlab.com/slof/slof>`_ (Slimline Open Firmware) is an
implementation of the `IEEE 1275-1994, Standard for Boot (Initialization
Configuration) Firmware: Core Requirements and Practices
<https://standards.ieee.org/standard/1275-1994.html>`_.
diff --git a/hw/pci-host/meson.build b/hw/pci-host/meson.build
index 86b754d0b0..3217e7e912 100644
--- a/hw/pci-host/meson.build
+++ b/hw/pci-host/meson.build
@@ -44,5 +44,7 @@ specific_ss.add(when: 'CONFIG_PCI_POWERNV', if_true: files(
'pnv_phb3_pbcq.c',
'pnv_phb4.c',
'pnv_phb4_pec.c',
+ 'pnv_phb5.c',
+ 'pnv_phb5_pec.c',
'pnv_phb.c',
))
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 396bc47817..705a5bcf07 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -1721,11 +1721,6 @@ static const TypeInfo pnv_phb4_type_info = {
}
};
-static const TypeInfo pnv_phb5_type_info = {
- .name = TYPE_PNV_PHB5,
- .parent = TYPE_PNV_PHB4,
- .instance_size = sizeof(PnvPHB4),
-};
static void pnv_phb4_root_bus_get_prop(Object *obj, Visitor *v,
const char *name,
@@ -1794,7 +1789,6 @@ static void pnv_phb4_register_types(void)
{
type_register_static(&pnv_phb4_root_bus_info);
type_register_static(&pnv_phb4_type_info);
- type_register_static(&pnv_phb5_type_info);
type_register_static(&pnv_phb4_iommu_memory_region_info);
}
diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c
index 58ec14ec2f..ee5cdc3e45 100644
--- a/hw/pci-host/pnv_phb4_pec.c
+++ b/hw/pci-host/pnv_phb4_pec.c
@@ -394,67 +394,9 @@ static const TypeInfo pnv_pec_type_info = {
}
};
-/*
- * POWER10 definitions
- */
-static uint32_t pnv_phb5_pec_xscom_cplt_base(PnvPhb4PecState *pec)
-{
- return PNV10_XSCOM_PEC_NEST_CPLT_BASE + XPEC_PCI_CPLT_OFFSET * pec->index;
-}
-
-static uint32_t pnv_phb5_pec_xscom_pci_base(PnvPhb4PecState *pec)
-{
- return PNV10_XSCOM_PEC_PCI_BASE + 0x1000000 * pec->index;
-}
-
-static uint32_t pnv_phb5_pec_xscom_nest_base(PnvPhb4PecState *pec)
-{
- /* index goes down ... */
- return PNV10_XSCOM_PEC_NEST_BASE - 0x1000000 * pec->index;
-}
-
-/*
- * PEC0 -> 3 stacks
- * PEC1 -> 3 stacks
- */
-static const uint32_t pnv_phb5_pec_num_stacks[] = { 3, 3 };
-
-static void pnv_phb5_pec_class_init(ObjectClass *klass, const void *data)
-{
- PnvPhb4PecClass *pecc = PNV_PHB4_PEC_CLASS(klass);
- static const char compat[] = "ibm,power10-pbcq";
- static const char stk_compat[] = "ibm,power10-phb-stack";
-
- pecc->xscom_cplt_base = pnv_phb5_pec_xscom_cplt_base;
- pecc->xscom_nest_base = pnv_phb5_pec_xscom_nest_base;
- pecc->xscom_pci_base = pnv_phb5_pec_xscom_pci_base;
- pecc->xscom_nest_size = PNV10_XSCOM_PEC_NEST_SIZE;
- pecc->xscom_pci_size = PNV10_XSCOM_PEC_PCI_SIZE;
- pecc->compat = compat;
- pecc->compat_size = sizeof(compat);
- pecc->stk_compat = stk_compat;
- pecc->stk_compat_size = sizeof(stk_compat);
- pecc->version = PNV_PHB5_VERSION;
- pecc->phb_type = TYPE_PNV_PHB5;
- pecc->num_phbs = pnv_phb5_pec_num_stacks;
-}
-
-static const TypeInfo pnv_phb5_pec_type_info = {
- .name = TYPE_PNV_PHB5_PEC,
- .parent = TYPE_PNV_PHB4_PEC,
- .instance_size = sizeof(PnvPhb4PecState),
- .class_init = pnv_phb5_pec_class_init,
- .class_size = sizeof(PnvPhb4PecClass),
- .interfaces = (const InterfaceInfo[]) {
- { TYPE_PNV_XSCOM_INTERFACE },
- { }
- }
-};
-
static void pnv_pec_register_types(void)
{
type_register_static(&pnv_pec_type_info);
- type_register_static(&pnv_phb5_pec_type_info);
}
type_init(pnv_pec_register_types);
diff --git a/hw/pci-host/pnv_phb5.c b/hw/pci-host/pnv_phb5.c
new file mode 100644
index 0000000000..c3f2e16ce6
--- /dev/null
+++ b/hw/pci-host/pnv_phb5.c
@@ -0,0 +1,23 @@
+/*
+ * QEMU PowerPC PowerNV (POWER10) PHB5 model
+ *
+ * Copyright (c) 2018-2026, IBM Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "hw/pci-host/pnv_phb4.h"
+
+static const TypeInfo pnv_phb5_type_info = {
+ .name = TYPE_PNV_PHB5,
+ .parent = TYPE_PNV_PHB4,
+ .instance_size = sizeof(PnvPHB4),
+};
+
+static void pnv_phb5_register_types(void)
+{
+ type_register_static(&pnv_phb5_type_info);
+}
+
+type_init(pnv_phb5_register_types);
diff --git a/hw/pci-host/pnv_phb5_pec.c b/hw/pci-host/pnv_phb5_pec.c
new file mode 100644
index 0000000000..488ccbfb12
--- /dev/null
+++ b/hw/pci-host/pnv_phb5_pec.c
@@ -0,0 +1,77 @@
+/*
+ * QEMU PowerPC PowerNV (POWER10) PHB5 PEC model
+ *
+ * Copyright (c) 2018-2026, IBM Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "hw/pci-host/pnv_phb4.h"
+#include "hw/ppc/pnv_xscom.h"
+
+#define XPEC_PCI_CPLT_OFFSET 0x1000000ULL
+
+/*
+ * POWER10 definitions
+ */
+static uint32_t pnv_phb5_pec_xscom_cplt_base(PnvPhb4PecState *pec)
+{
+ return PNV10_XSCOM_PEC_NEST_CPLT_BASE + XPEC_PCI_CPLT_OFFSET * pec->index;
+}
+
+static uint32_t pnv_phb5_pec_xscom_pci_base(PnvPhb4PecState *pec)
+{
+ return PNV10_XSCOM_PEC_PCI_BASE + 0x1000000 * pec->index;
+}
+
+static uint32_t pnv_phb5_pec_xscom_nest_base(PnvPhb4PecState *pec)
+{
+ /* index goes down ... */
+ return PNV10_XSCOM_PEC_NEST_BASE - 0x1000000 * pec->index;
+}
+
+/*
+ * PEC0 -> 3 stacks
+ * PEC1 -> 3 stacks
+ */
+static const uint32_t pnv_phb5_pec_num_stacks[] = { 3, 3 };
+
+static void pnv_phb5_pec_class_init(ObjectClass *klass, const void *data)
+{
+ PnvPhb4PecClass *pecc = PNV_PHB4_PEC_CLASS(klass);
+ static const char compat[] = "ibm,power10-pbcq";
+ static const char stk_compat[] = "ibm,power10-phb-stack";
+
+ pecc->xscom_cplt_base = pnv_phb5_pec_xscom_cplt_base;
+ pecc->xscom_nest_base = pnv_phb5_pec_xscom_nest_base;
+ pecc->xscom_pci_base = pnv_phb5_pec_xscom_pci_base;
+ pecc->xscom_nest_size = PNV10_XSCOM_PEC_NEST_SIZE;
+ pecc->xscom_pci_size = PNV10_XSCOM_PEC_PCI_SIZE;
+ pecc->compat = compat;
+ pecc->compat_size = sizeof(compat);
+ pecc->stk_compat = stk_compat;
+ pecc->stk_compat_size = sizeof(stk_compat);
+ pecc->version = PNV_PHB5_VERSION;
+ pecc->phb_type = TYPE_PNV_PHB5;
+ pecc->num_phbs = pnv_phb5_pec_num_stacks;
+}
+
+static const TypeInfo pnv_phb5_pec_type_info = {
+ .name = TYPE_PNV_PHB5_PEC,
+ .parent = TYPE_PNV_PHB4_PEC,
+ .instance_size = sizeof(PnvPhb4PecState),
+ .class_init = pnv_phb5_pec_class_init,
+ .class_size = sizeof(PnvPhb4PecClass),
+ .interfaces = (const InterfaceInfo[]) {
+ { TYPE_PNV_XSCOM_INTERFACE },
+ { }
+ }
+};
+
+static void pnv_phb5_pec_register_types(void)
+{
+ type_register_static(&pnv_phb5_pec_type_info);
+}
+
+type_init(pnv_phb5_pec_register_types);
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 62812f22f8..afb6019b10 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -803,9 +803,13 @@ static void pnv_reset(MachineState *machine, ResetType type)
mpipl_write_succeeded = do_mpipl_write(pnv);
}
- /* Regenerate device tree */
- fdt = pnv_dt_create(machine);
- _FDT((fdt_pack(fdt)));
+ /* Only create new dt if not provided in -dtb */
+ if (!machine->dtb) {
+ fdt = pnv_dt_create(machine);
+ _FDT((fdt_pack(fdt)));
+ } else {
+ fdt = machine->fdt;
+ }
/*
* If it's a MPIPL boot, add the "mpipl-boot" property, and reset the
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index a512d4fa64..b123b4cc1c 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -515,6 +515,11 @@ uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset)
return ns_to_tb(tb_env->tb_freq, vmclk) + tb_offset;
}
+int64_t cpu_ppc_load_tb_offset(CPUPPCState *env)
+{
+ return env->tb_env->tb_offset;
+}
+
uint64_t cpu_ppc_load_tbl (CPUPPCState *env)
{
ppc_tb_t *tb_env = env->tb_env;
diff --git a/pc-bios/README b/pc-bios/README
index 4818272968..2f8a565245 100644
--- a/pc-bios/README
+++ b/pc-bios/README
@@ -14,7 +14,7 @@
- SLOF (Slimline Open Firmware) is a free IEEE 1275 Open Firmware
implementation for certain IBM POWER hardware. The sources are at
https://gitlab.com/slof/slof, and the image currently in qemu is
- built from git tag qemu-slof-20251026.
+ built from git tag qemu-slof-20260627.
- VOF (Virtual Open Firmware) is a minimalistic firmware to work with
-machine pseries,x-vof=on. When enabled, the firmware acts as a slim shim and
diff --git a/pc-bios/slof.bin b/pc-bios/slof.bin
index 39b9248967..6a6d944b07 100644
--- a/pc-bios/slof.bin
+++ b/pc-bios/slof.bin
Binary files differ
diff --git a/roms/SLOF b/roms/SLOF
-Subproject b7f755248e2dcc56c02634d288e1c0ff7e0ce1c
+Subproject 47457c9078a217150aa1634f2657e6804fbde46
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 057c54bbb8..cbd5964b1a 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1693,6 +1693,7 @@ void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value);
void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value);
uint64_t cpu_ppc_load_purr(CPUPPCState *env);
void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value);
+int64_t cpu_ppc_load_tb_offset(CPUPPCState *env);
#if !defined(CONFIG_USER_ONLY)
target_ulong load_40x_pit(CPUPPCState *env);
void store_40x_pit(CPUPPCState *env, target_ulong val);
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index a02187ce5a..8cab5e12b6 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7620,8 +7620,9 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
#if !defined(CONFIG_USER_ONLY)
if (env->tb_env) {
qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
- " DECR " TARGET_FMT_lu "\n", cpu_ppc_load_tbu(env),
- cpu_ppc_load_tbl(env), cpu_ppc_load_decr(env));
+ " DECR " TARGET_FMT_lu " TB_OFFSET %016" PRId64 "\n",
+ cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env),
+ cpu_ppc_load_decr(env), cpu_ppc_load_tb_offset(env));
}
#else
qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 "\n", cpu_ppc_load_tbu(env),
diff --git a/tests/functional/ppc64/test_powernv.py b/tests/functional/ppc64/test_powernv.py
index 0ea6c93e42..b5b2f0d158 100755
--- a/tests/functional/ppc64/test_powernv.py
+++ b/tests/functional/ppc64/test_powernv.py
@@ -27,6 +27,11 @@ class PowernvMachine(LinuxKernelTest):
'buildroot/qemu_ppc64le_powernv8-2025.02/rootfs.ext2'),
'aee2192b692077c4bde31cb56ce474424b358f17cec323d5c94af3970c9aada2')
+ # testdtb for power11, which contains string "hello world" in command line
+ ASSET_SAMPLE_DTB = Asset(
+ ('https://github.com/roz3x/qemu/raw/refs/heads/sample-dtb/qemu-powernv11.dtb'),
+ 'ea1271516264eea1eb58a067a99d0c2ca9528be8dc7d4e46bb2d5ae0d42fc568')
+
def do_test_linux_boot(self, command_line = KERNEL_COMMON_COMMAND_LINE):
self.require_accelerator("tcg")
kernel_path = self.ASSET_KERNEL.fetch()
@@ -104,6 +109,20 @@ class PowernvMachine(LinuxKernelTest):
# Device detection output driven by udev probing is sometimes cut off
# from console output, suspect S14silence-console init script.
+ def test_ppc64_powernv_external_dtb(self):
+ self.set_machine('powernv11')
+ self.require_accelerator("tcg")
+
+ kernel_path = self.ASSET_KERNEL.fetch()
+ sample_dtb_path = self.ASSET_SAMPLE_DTB.fetch()
+ self.vm.set_console()
+ self.vm.add_args('-kernel', kernel_path,
+ '-dtb', sample_dtb_path)
+ self.vm.launch()
+
+ # check if custom dtb is reflected or not
+ wait_for_console_pattern(self, "Kernel command line: hello world", self.panic_message)
+
def test_powernv8(self):
self.set_machine('powernv8')
self.do_test_ppc64_powernv('P8')
generated by cgit v1.2.3 (git 2.39.1) at 2026-07-07 01:42:39 +0000