diff options
| author | Maulik Shah <maulik.shah@oss.qualcomm.com> | 2026-04-24 12:01:24 +0530 |
|---|---|---|
| committer | Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> | 2026-07-27 16:24:23 +0200 |
| commit | 1860fb0be224dec0e4d170f46d1cbbc77e25e09e (patch) | |
| tree | 79a808d48ee654ba4e43104c2d21022519569c90 | |
| parent | 82c3edf8701154e2768973ebd4c0d2f3bd29621e (diff) | |
| download | linux-next-1860fb0be224dec0e4d170f46d1cbbc77e25e09e.tar.gz linux-next-1860fb0be224dec0e4d170f46d1cbbc77e25e09e.zip | |
pinctrl: qcom: Add irq_get/set_irqchip_state() for msm gpio irqchip
MPM irqchip monitors the interrupts during SoC sleep state and after wakeup
replays the edge interrupt by making it pending at respective irqchip by
invoking irq_set_irqchip_state() API. The msm gpio irqchip however do not
implement this function making it impossible to replay the gpio interrupt
on any MPM irqchip based SoC.
Add the missing irq_get/set_irqchip_state() APIs. Implement only
IRQCHIP_STATE_PENDING case which MPM irqchip uses.
Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com>
Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com>
Acked-by: Linus Walleij <linusw@kernel.org>
Reviewed-by: Navya Malempati <navya.malempati@oss.qualcomm.com>
Link: https://patch.msgid.link/20260424-pinctrl_irqchip_states-v1-1-85286f078916@oss.qualcomm.com
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
| -rw-r--r-- | drivers/pinctrl/qcom/pinctrl-msm.c | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 838969186185..3cb48ba31b78 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -1313,6 +1313,43 @@ static int msm_gpio_irq_set_affinity(struct irq_data *d, return -EINVAL; } +static int msm_gpio_irq_set_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, bool val) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; + + if (which != IRQCHIP_STATE_PENDING) + return -EINVAL; + + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return -EINVAL; + + msm_writel_intr_status(val, pctrl, g); + + return 0; +} + +static int msm_gpio_irq_get_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, bool *val) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; + + if (which != IRQCHIP_STATE_PENDING) + return -EINVAL; + + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return -EINVAL; + + g = &pctrl->soc->groups[d->hwirq]; + *val = msm_readl_intr_status(pctrl, g); + + return 0; +} + static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); @@ -1401,6 +1438,8 @@ static const struct irq_chip msm_gpio_irq_chip = { .irq_request_resources = msm_gpio_irq_reqres, .irq_release_resources = msm_gpio_irq_relres, .irq_set_affinity = msm_gpio_irq_set_affinity, + .irq_set_irqchip_state = msm_gpio_irq_set_irqchip_state, + .irq_get_irqchip_state = msm_gpio_irq_get_irqchip_state, .irq_set_vcpu_affinity = msm_gpio_irq_set_vcpu_affinity, .flags = (IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED | |