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| author | Damon Ding <damon.ding@rock-chips.com> | 2026-06-05 10:23:03 +0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2026-07-24 21:30:27 +0200 |
| commit | ede2ee37f0a445cacbf24760f53befa10f64994a (patch) | |
| tree | 9706fcb73d9c1bb8f3cd41905edc7a7632fd5388 | |
| parent | dfe078755706ed50651ebbe0442843ecd4ae8389 (diff) | |
| download | linux-next-ede2ee37f0a445cacbf24760f53befa10f64994a.tar.gz linux-next-ede2ee37f0a445cacbf24760f53befa10f64994a.zip | |
arm64: dts: rockchip: Add missing hclk for RK3588 eDP0
Add the required HCLK_VO1 bus clock to RK3588 eDP0 node with
corresponding clock-name "hclk". This clock is necessary for the
eDP controller to access video output GRF and work properly.
Previously the clock was enabled implicitly via GRF phandle
reference. Add it explicitly now to align with updated binding.
Fixes: dc79d3d5e7c7 ("arm64: dts: rockchip: Add eDP0 node for RK3588")
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Link: https://patch.msgid.link/20260605022305.3058853-2-damon.ding@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index fc1fdbfd3162..376ad04e0786 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1910,8 +1910,8 @@ edp0: edp@fdec0000 { compatible = "rockchip,rk3588-edp"; reg = <0x0 0xfdec0000 0x0 0x1000>; - clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>; - clock-names = "dp", "pclk"; + clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>, <&cru HCLK_VO1>; + clock-names = "dp", "pclk", "hclk"; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; phys = <&hdptxphy0>; phy-names = "dp"; |