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| author | Vladimir Zapolskiy <vz@mleia.com> | 2026-01-10 03:45:24 +0200 |
|---|---|---|
| committer | Vladimir Zapolskiy <vz@mleia.com> | 2026-01-10 03:47:36 +0200 |
| commit | 2940a49ab7e31e9fc4f43637dc9ef75b5e8951d4 (patch) | |
| tree | cb9fbfa5dbeb76a4eef7151c2014556214e93d72 | |
| parent | 71630e581a0e34c03757f5c1706f57c853b92555 (diff) | |
| download | linux-2940a49ab7e31e9fc4f43637dc9ef75b5e8951d4.tar.gz linux-2940a49ab7e31e9fc4f43637dc9ef75b5e8951d4.zip | |
arm: dts: lpc32xx: add interrupts property to Motor Control PWM
Motor Control PWM shares an interrupt line with TIMER4 on MIC interrupt
controller, the interrupt serves as period (timer limit), pulse-width (match)
and capture event interrupt.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
| -rw-r--r-- | arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 7fa91d1ac9ea..e94df78def18 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -322,6 +322,7 @@ mpwm: pwm@400e8000 { compatible = "nxp,lpc3220-motor-pwm"; reg = <0x400e8000 0x78>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; clocks = <&clk LPC32XX_CLK_MCPWM>; #pwm-cells = <3>; status = "disabled"; |