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44 hoursMerge tag 'firmware-20260704-pull-request' of https://gitlab.com/kraxel/qemu ↵HEADmasterStefan Hajnoczi
into staging igvm: add device tree support # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEoDKM/7k6F6eZAf59TLbY7tPocTgFAmpIkaMACgkQTLbY7tPo # cTg4NA/8CB9HEZG6kKV1fh/7N5ev0iL5S1K3HCxKYcHoyMfkkhDvORSa5oF8gYoP # HiJC4D+8X+523YFOzvxsaRgTC0J6iRucktIz2PNHBpy7npcQpiRjI1l9Z4FPEH0b # iPSuKgpliOYIUi/ckeTKK4q2GwYsxIaLhu/uGsEr10cCf62JkXigkc5t1ZXa/ggv # HYBVNE9HM6CG6SWQKEqrfuSYex8Xa4+x/euzsAgDkuEBfYykHt4duDD1iObEJ6Cy # 3UXodgkcLrnz5baWbtTNjmVRsQfyjtD7/kfo4yPNvzC80UIjdvxg4COXF6YxId5P # gDBWl8bY9rqYah8zQ4QzxbVZ7HWJDCILLWc0O2Mlw70KdUQ7g5JA1Gjf6Ms5YgB6 # PEH+rJ9ir09MJ9Z7AWRo3Ry91opDGrKUos2maQHdf8AADV9afmJVQ1frnDgUjF/3 # PXZVVCSpVoLBP5GLT+2l60qFYzJPqd/HsK5cWGaZEJyfvejrZjEVI6l9FliQFJ9l # HiLEo2yhWVtRzruy7Uv16tU42xODmDMBKU12HZfQLvYbKUaBf24YpLiBprEzUM72 # snXGhZX7wQl6ghQ7mxdLncECRRvFwuknZPeLBPWyp6rm5IuTvxkhRtgCHS4RFYbr # 7NDjzJ3/gg9YXy3z0cJjRkaBfJvwdYTUTpuq0yDVOfNL53L0jbA= # =7c95 # -----END PGP SIGNATURE----- # gpg: Signature made Sat 04 Jul 2026 06:52:51 CEST # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * tag 'firmware-20260704-pull-request' of https://gitlab.com/kraxel/qemu: igvm: add device tree parameter support igvm: use idiomatic meson conditional for IGVM build files igvm: Report error on missing parameter area in directive handlers Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
4 daysMerge tag 'pull-qobject-2026-07-02' of https://repo.or.cz/qemu/armbru into ↵Stefan Hajnoczi
staging QObject patches for 2026-07-02 # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCgAwFiEENUvIs9frKmtoZ05fOHC0AOuRhlMFAmpGUpgSHGFybWJydUBy # ZWRoYXQuY29tAAoJEDhwtADrkYZTA3wP/jXwy30ND7OQE5HErDKp4priCm9cMPcR # 30FxOS+E9bAT6KCDmnUqRVELebGn0x3gz9MXWO8qQcU4MHneN4M/42Dh/oa1t+xd # Zva2rIfVW1FHPvzEfsKsUFPq1LaY+uM9XW2DdEjyv11RoMZwVHiWseURXwB2HNLH # HNfxBOlGa8VTvI5kpRafN+DNRjeMEWcIXqZRHr51GeFfc6av0CTUYM2xdwRQTw3m # GQGDvLIllxb9STwnSKieBdkCpBGSwffcjJipt7VmvORYNsi3pcJgAhWFzM9UWqPp # ZENwziphyd/4XLAC4EaMlXnXlAzLJh+H7+th6Ylirkjo1sULO9cCFbYcANqljLdT # GIIafRoe4zuZp1gFPgT51nA53Adzd1TWCT462R1uzbVJxoEdthsYVB7WMamBJySA # MuuMjq4JVeROBgDbO/X7+EnzmI0torT24XpFxFjfBGb9zSnG7YRzSSf8sDQIwir+ # tlh0e6LzsVJckJ0IUAjglLKb49QUnmzrSx8+6LCH0iFMkHWwXdtd5Vyk5SofIXIy # Dc6t2qH8USkOjwgs5vKdr9m8LEv2iELegpanmZDTd+zIEFR1WP1SRiirmkoD7QJY # 0zK3gabC5uUpcfKx6EE2UXWpFW/tVDjMUN43QoL48/pVDuYUcqXJ8y2DEqjHV4Sd # O5wd3ZOFdvVc # =jshD # -----END PGP SIGNATURE----- # gpg: Signature made Thu 02 Jul 2026 13:59:20 CEST # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * tag 'pull-qobject-2026-07-02' of https://repo.or.cz/qemu/armbru: json-parser: add location to JSON parsing errors json-streamer: do not heap-allocate JSONToken json-streamer: remove token queue json-streamer: make brace/bracket count unsigned json-streamer: reuse parser json-parser: replace with a push parser qobject/json-writer: preallocate output buffer Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
5 daysMerge tag 'dump-pr-v1' of https://gitlab.com/marcandre.lureau/qemu into stagingStefan Hajnoczi
Dump patches for 2026-06-30 To: qemu-devel@nongnu.org Cc: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEh6m9kz+HxgbSdvYt2ujhCXWWnOUFAmpD3PsACgkQ2ujhCXWW # nOUW8g//W75y5yaaujNXQ/tqRmIGpVKuB1rC5QXJgRYQlpEIh21tPeHHUUFpOSgU # llgo2NZM4fqX450vBDU2L6J+qtGc7Q6tm3EKlAe+dZeIlqCcrvHDTGHLq83pCGZQ # LbABgwnxRcK+BOmSH/LdsP33dFYWBMMwSNZ0P/C986pAs5m/Ji6oz7OI1hRvv5E/ # /HjwJLaXbCyOesWicKpFmN2wiwi3GRiiwI5mBBrue3mmkTvHzb52Pas/B+jT/q/G # WzIKMYUAwlvYIg2NiWcr1r5UAaXohq4Z4O8jWSpXFoZbg24B5GfmPzg2/mWKtFs1 # UN5J5soqHA/7DV+hDK6v3dPWFnjAMe5PtxjtFdxlt7z5B0LS2hnwHW3tbZtWIhbV # cFUheXb+ySVw6h0ieK/Ym5k76tExvWHMDfacBHD6oo+ikiOxifCdSSvADYYvnpIU # ySfjfnEwXg2F/TrsL1o4uotcHeyONJEjy/V6l+pgOATyTGfUvUk0PCRwGNNBhshx # fZVbP8TSFw3NmS5j86dPUa8hyX1AZPRwSnxPzN/iOnCGigyPjJ3clcGQZ1YGwnip # KvDXQjmoirJutwEWVd1HZmGnWUqAfrJuselSvER5dWFEKnukbn7wmkIQx3aixZT4 # 1/AUNqPsMNREDTMHN6KCAK7mj7024Gq2Gmupu7aYpdZZtPHUXPA= # =NMTJ # -----END PGP SIGNATURE----- # gpg: Signature made Tue 30 Jun 2026 17:12:59 CEST # gpg: using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5 # gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [full] # gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [full] # Primary key fingerprint: 87A9 BD93 3F87 C606 D276 F62D DAE8 E109 7596 9CE5 * tag 'dump-pr-v1' of https://gitlab.com/marcandre.lureau/qemu: dump: fix misleading VMCOREINFO phys_base parse error tests/qtest/dump: cover win-dmp availability via vmcoreinfo tests/qtest/dump: reject win-dmp without vmcoreinfo tests/qtest: add dump-guest-memory test dump: make win_dump_available() check vmcoreinfo for a Windows dump header system/cpus: refuse memsave/pmemsave while guest RAM is being migrated dump: refuse dump-guest-memory while guest RAM is being migrated migration: add migration_guest_ram_loading() helper Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
5 daysjson-parser: add location to JSON parsing errorsPaolo Bonzini
Now that all calls to parse_error have a token, add the line and column to the message. As far as I can see the two important TODOs (better errors and better EOI handling) are done, and the others (token range information and "parsed size"?) do not really matter or are handled better by json-streamer.c. So remove the list, which had sat unchanged since 2009. This needs some adjustments to provide a good x and y for error messages. First of all, they switch from zero-based to one-based, which is safe because they were both sitting unused. Second, right now the x and y are those of the *last* character in the token. Modify json-lexer.c to freeze tok->x and tok->y at the first character added to the GString. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20260626101727.1727389-7-pbonzini@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
5 daysjson-streamer: remove token queuePaolo Bonzini
Now fully exploit the push parser, feeding it one token at a time without having to wait until braces and brackets are balanced. While the nesting counts are retained for error recovery purposes, the system can now report the first parsing error without waiting for parentheses to be balanced. This also means that JSON_ERROR can be handled in json-parser.c, not json-streamer.c. After reporting the error, json-streamer.c then enters an error recovery mode where subsequent errors are suppressed. This mimics the previous error reporting behavior, but it provides prompt feedback on parsing errors. As an example, here is an example interaction with qemu-ga. BEFORE (error reported only once braces are balanced): >> {"execute":foo >> } << {"error": {"class": "GenericError", "desc": "JSON parse error, invalid keyword 'foo'"}} >> {"execute":"somecommand"} << {"error": {"class": "CommandNotFound", "desc": "The command somecommand has not been found"}} AFTER (error reported immediately, but similar error recovery as before): >> {"execute":foo << {"error": {"class": "GenericError", "desc": "JSON parse error, invalid keyword 'foo'"}} >> } >> {"execute":"somecommand"} << {"error": {"class": "CommandNotFound", "desc": "The command somecommand has not been found"}} Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20260626101727.1727389-5-pbonzini@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> [Token size limit check off-by-one fixed] Signed-off-by: Markus Armbruster <armbru@redhat.com>
5 daysjson-streamer: make brace/bracket count unsignedPaolo Bonzini
It makes no sense to let brace_count and bracket_count go negative, also because it immediately ends error recovery and sets them both back to zero. Instead set them to zero *before* choosing whether to process the token queue; this makes it possible to have the fields as unsigned. Note that JSON_END_OF_INPUT now forces the parentheses to appear balanced, so that the queue is emptied and an error is reported; hence, the "type != JSON_END_OF_INPUT" condition can be removed. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20260626101727.1727389-4-pbonzini@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> [Comment tweaked] Signed-off-by: Markus Armbruster <armbru@redhat.com>
5 daysjson-streamer: reuse parserPaolo Bonzini
The push parser can be reset, so reuse it when the json-streamer detects a completed toplevel object. Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20260626101727.1727389-3-pbonzini@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
5 daysjson-parser: replace with a push parserPaolo Bonzini
In order to avoid stashing all the tokens corresponding to a JSON value, embed the parsing stack and state machine in JSONParser. This is more efficient and allows for more prompt error recovery; it also does not make the code substantially larger than the current recursive descent parser, though the state machine is probably a bit harder to follow. The stack consists of QLists and QDicts corresponding to open brackets and braces, plus optionally a QString with the current key on top of each QDict. After each value is parsed, it is added to the top array or dictionary or, if the stack is empty, json_parser_feed returns the complete QObject. For now, json-streamer.c keeps tracking the tokens up until braces and brackets are balanced, and then shoves the whole queue of tokens into the push parser. The only logic change is that JSON_END_OF_INPUT always triggers the emptying of the queue; the parser takes notice and checks that there is nothing on the stack. Not using brace_count and bracket_count for this is the first step towards improved separation of concerns between json-parser.c and json-streamer.c. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20260626101727.1727389-2-pbonzini@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> [Minor comment improvements] Signed-off-by: Markus Armbruster <armbru@redhat.com>
5 daysigvm: Report error on missing parameter area in directive handlersLuigi Leonardi
Parameter areas are how an IGVM file tells QEMU to allocate buffers for runtime information the guest needs — VP count, memory map, MADT and so on. Usage directives reference a parameter area by index to tell QEMU where to write each piece of data. If the index doesn't match any declared parameter area, the data has nowhere to go and should be treated as an error. The directive handlers that look up a parameter area all return 0 (success) when `qigvm_find_param_entry()` can't find it. Therefore, the load succeeds but the guest never gets the expected parameters. Note that the IGVM library already validates parameter area indices when the file is loaded, so this path should only be reachable with a malformed file that bypassed library validation. This is defensive programming against that case. Report the error with error_setg() and return -1 instead. Signed-off-by: Luigi Leonardi <leonardi@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Message-ID: <20260626-microvm_device_tree-v6-1-9cd13cf057e2@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
5 daysMerge tag 'pull-riscv-to-apply-20260701' of ↵Stefan Hajnoczi
https://github.com/alistair23/qemu into staging RISC-V PR for 11.1 * Fix IMSIC CSR write and add tests * Parametrise debug trigger number * Add 'svbare' satp-mode * Fix RINTC PLIC context ID for KVM * Avoid abort when reading vtype before env->xl is set * Skip reset for KVM irqchip * Skip FP/Vector sync on KVM_PUT_RUNTIME_STATE * More FDT cleanups (PLIC) * Make FCTL.BE in IOMMU read only 0 * Check DC.TC reserved bits in IOMMU * Apply UXL WARL handling to vsstatus * Set cmd_ill IOFENCE.C if rsvp bits are set in IOMMU * Set RISCV_IOMMU_FQ_HDR_PV appropriately * Fix MSI MRIF IOMMU interrupt-pending offset * Report QEMU CPU archid as 42 * Check PMP before updating PTE * Add the Tenstorrent Atlantis machine # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmpE6SoACgkQr3yVEwxT # gBOxNQ//bI4BvnT65Kd2UNMgtAwwPPcehpsyPzC2S3BcflniXQL+fV6sQ7IreKta # 6dclp/v5v+yhbB4bd/E1s/UPOF3YD4A9noUFifIhymBkafmqA4YRNsvPByeGiSD8 # xVkHhX5qUT9NW5wKnivEDjO8mndBMRm5YEXQ6uT5ulUsZr3Ir8wPOCJITZ8ZqKwb # 6dbbXStf1aTIBzu53KaNhNpi9DQqKV5UeV7CiSuhuwWU0qmVg1RAZMg9X3oB80rE # WpWqH0rg9Z0Cn+3XL+oKSzbLD5SrrTV+Ohq+K8zT2rEk+hIXOE3shAPm2xfTT9Q2 # g65nBOf2UmNWeHlvn3XC2LtmIWq10/A78ogGgm4XwHx8TXIeA2KIKboyS8T37XAb # NwUllq9LRtfDVtDevpiTn6t7Oa7TC8zrxDJTT1rg/p+3D6MdfkonifwJJgVAwfuG # NF7R2iePKPQliWr1hi6W+ghzQMRFXgNBwUNOL39/BQguy5IqvNmSk6ovhl8IFocf # aXGh9U35DqgrsUvMa/7Fgf4uI2QNhERBGJrHfL0SPZ82sKb5CTrMw9URwg0DFnEF # 8v/zQ9xL4eF0uZn0OtaNlLXRCblDxcHSgecwix9Vip5toFIc1P8ar9FX98Zd/H5l # UD/a3ENtiwb6hnKhZ+45iM/NIFJeUK7A0944VnQzx00tA06wJLw= # =a4hl # -----END PGP SIGNATURE----- # gpg: Signature made Wed 01 Jul 2026 12:17:14 CEST # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20260701' of https://github.com/alistair23/qemu: (39 commits) hw/riscv/riscv-iommu.c: always fault with SADE=0 and A=0 hw/riscv/atlantis: Add some i2c peripherals hw/riscv/atlantis: Integrate i2c controllers hw/i2c: Add DesignWare I2C Controller tests/functional/riscv64: Add tt-atlantis tests hw/riscv/atlantis: Ensure OpenSBI has a non-zero next_addr hw/riscv: Add Tenstorrent Atlantis machine target/riscv: tt-ascalon: Enable Zkr extension hw/riscv/aia: Configure stride for the M-mode IMSIC hw/riscv/aia: Provide number of irq sources hw/riscv/virt: Move AIA initialisation to helper file hw/riscv/boot: Account for discontiguous memory when loading firmware hw/riscv/boot: Describe discontiguous memory in boot_info target/riscv: Check PMP before updating PTE target/riscv: Report QEMU CPU archid as 42 hw/riscv/riscv-iommu.c: fix MSI MRIF interrupt-pending offset hw/riscv/riscv-iommu.c: set RISCV_IOMMU_FQ_HDR_PV appropriately hw/riscv/riscv-iommu: set cmd_ill IOFENCE.C rsvp bits are set target/riscv: Apply UXL WARL handling to vsstatus hw/riscv/riscv-iommu: check DC.TC reserved bits ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
5 daysMerge tag 'pull-ufs-20260701' of https://gitlab.com/jeuk20.kim/qemu into stagingStefan Hajnoczi
ufs queue # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEUBfYMVl8eKPZB+73EuIgTA5dtgIFAmpEoa0ACgkQEuIgTA5d # tgLm1Q//Vqj6g2tNoiGqfIhuuUGjYiMifyfRzF9ZGVKBUwXeduaJ0gXE05duVbCx # FZyheWVUzvovDyWMgvpk0NwBz0WIEUWmWj9GtKnGMpRU9cFxATlUuFbYU+tY2aZC # dt6Ck3saRrVDvcrETucgkzL8HuEehXtZCfnqNmEkggXuhuaPJnkm8bKzs5fxapF/ # QT4T1j2RTFkWtHTfvnXrQiDmqVTGpRlI2USjCdCd3RUFxnKbFZJ8EcLJVAYPGrBR # RRi2eY4M2hCbZnNctpYfj86GltbFypnPfuhT+HVbIsue9+FEWScTa7BGeWpZETjJ # Drj19XAWbponVYXya57Me7I83b3+UJjSQe2eH4OGB0iTeqAlTQggAkmofzHWqD50 # +OyY6zT0TkPDpLmcBUbIwk94A+qV9iVETOLc0W2jX5CYrawD+lI9tAKeGtO6lv8c # Os5dy1vHvulDhd8H4tuCyepwLmU8KETZMDbSRwyQfgBKJx1eknqY0ITKynXbalIr # y1y5SzW+KnvB/2Dap3wfbYxpT441PEMlpN9cQslEALP+oHg80g+DdR47VJVJIkPM # 4ZR9T8LN8bm0hyzGVooQ0VpeKTA5ualAr9f0kT40a/8MuhedsXSy9XQBe9PYTiOe # 3MHqqPQFmwOXH6dzMUV44r0K9mW0QheBC9gLywq1yy4EIJ5DWMs= # =pbB1 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 01 Jul 2026 07:12:13 CEST # gpg: using RSA key 5017D831597C78A3D907EEF712E2204C0E5DB602 # gpg: Good signature from "Jeuk Kim <jeuk20.kim@samsung.com>" [unknown] # gpg: aka "Jeuk Kim <jeuk20.kim@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 5017 D831 597C 78A3 D907 EEF7 12E2 204C 0E5D B602 * tag 'pull-ufs-20260701' of https://gitlab.com/jeuk20.kim/qemu: hw/ufs: Populate cqe.task_tag for UFSHCI 4.1 tag decoding hw/ufs: Emulate DME_GET/SET for PA layer attributes Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
5 daysMerge tag 'pull-target-arm-20260629' of https://gitlab.com/pm215/qemu into ↵Stefan Hajnoczi
staging target-arm queue: * hw/timer/imx_epit: Replace DPRINTF with trace events target/arm: Enable SCTLR_EL1.EnFPM for user-only target/arm: Implement FEAT_SME_F8F32 target/arm: Implement FEAT_SSVE_AES target/arm: Implement FEAT_SME_F8F16 target/arm: GICv5: Fix some minor bugs target/arm: Add GPC3 granule bypass windows target/arm: Fix some minor timer related bugs hw/arm/sabrelite: Add FlexCAN emulation docs/system: add FEAT_ECV_POFF to the emulation list docs/system/arm/virt: Document accelerated SMMUv3 and Tegra241 CMDQV # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmpCXaQZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3nfkEACJkoMzHDyHcAiRdO8fK4o6 # zHP3f42UOnXTbX//Yga0PpxScWfvD8XbbOSeJRvpjuxl8nP8QF4/rF4b+atMy9Vl # MH0r/CWl9fZwQOSmjOLzgRGzXx0j9RPPpB/7eYTnKYImfOaEEaGvW4JqoBRE2Nbo # x5PaQjaqFQi76uGAJvALPgAPCgaK1DGbNDSRuH4RM7auLBWmSaoxdidiTDSBUqY0 # xsI/lU7t+/LLWirjP/QhM4mbxEc2DjENbguRHYlOqe5aHc6KdSmNj2B4/hTfyDON # c6APaAAPfCy3duL3JsvmwRZ8YM7zoUFEHysLjRxLWyiFfXZUIXPSMZaGpz88iyDV # Cbraw24K5tVVNvwQTKOpHYCnjNb4dZj1Zt/jdGIu16LQ8nsKgX2EJ6oh6lI85Q6n # d3Jbq+iLOy2r2r4CRTMIJYKZ2Bikkmyr+wZGO18nttnTVpWNzWVZtq4cutygr5vb # 0+5Lmr7YeYsdmIc1tpcJmlfmmo7dW987HyzK3/B65gPXV64w+a3eALRLPkMGevTT # MhG48151NEovHxfKqzsOMIixnPUKGPtAUbeKy/Ywv2ezKUmER19h/7nJ0lsa32pl # HYctGj4QeK4VjOO8E1q44ZIionhZFt+RHXBxxbiBzQBns/ryFBOQFEA3WzKi7rnd # a0v1M+AAK/UxmCjV7Sl0WA== # =OvGk # -----END PGP SIGNATURE----- # gpg: Signature made Mon 29 Jun 2026 13:57:24 CEST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20260629' of https://gitlab.com/pm215/qemu: (54 commits) docs/system/arm/virt: Document accelerated SMMUv3 and Tegra241 CMDQV target/arm: Enable FEAT_SME_F8F16 for -cpu max target/arm: Implement FVDOT (FP8 to FP16) target/arm: Rename FVDOT pattern target/arm: Implement FMOPA (widening, 2-way, FP8 to FP16) target/arm: Implement FDOT (multiple and indexed, FP8 to FP16) target/arm: Implement FDOT (multiple, multiple and single, FP8 to FP16) target/arm: Implement FMLAL (multiple and indexed, FP8 to FP16) target/arm: Implement FMLAL (multiple, multiple and single, FP8 to FP16) target/arm: Rename SME FMLAL/FMLSL patterns target/arm: Enable FADD/FSUB (half-precision) with FEAT_SME_F8F16 docs/system: add FEAT_ECV_POFF to the emulation list target/arm: trigger timer recalc on HCR:(E2H|TGE) changes target/arm: gate check on scr_el3 behind ARM_FEATURE_EL3 check target/arm: trigger timer recalc on SCR:ECVEN change target/arm: trigger timer recalculation when toggling CNTHCTL:ECV target/arm: split evaluation of CNTHCTL timer IRQ masks docs/arm/sabrelite: Mention FlexCAN support tests: Add qtests for FlexCAN hw/arm: Plug FlexCAN into FSL_IMX6 and Sabrelite ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
6 dayshw/riscv/atlantis: Integrate i2c controllersJoel Stanley
Add DesignWare I2C controllers to the tt-atlantis machine. Provide a fixed clock in the device tree so that the Linux driver probes without WARNing. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20260630024952.1520546-12-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/i2c: Add DesignWare I2C ControllerChris Rauer
Add a model for the Synopsys DesignWare Advanced I2C/SMBus Controller with sufficient functionality to be used by the Linux Designware I2C platform driver. This IP is used in the Tenstorrent Atlantis RISC-V SoC and will be added to the QEMU tt-atlantis machine. [npiggin: changelog, code cleanups and fixes as-per below link] Reviewed-by: Hao Wu <wuhaotsh@google.com> Signed-off-by: Chris Rauer <crauer@google.com> Link: https://lore.kernel.org/qemu-devel/20220110214755.810343-2-venture@google.com [jms: rebase and minor build fixes for class_init and reset callback] Link: https://lore.kernel.org/qemu-devel/20260507120524.111056-1-npiggin@gmail.com Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Corey Minyard <cminyard@mvista.com> Tested-by: Alano Song <AlanoSong@163.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20260630024952.1520546-11-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/riscv: Add Tenstorrent Atlantis machineJoel Stanley
The Tenstorrent Atlantis platform is a collaboration between Tenstorrent and CoreLab Technology. It is based on the Atlantis SoC, which includes the Ascalon-X CPU and other IP from Tenstorrent and CoreLab Technology. The Tenstorrent Ascalon-X is a high performance 64-bit RVA23 compliant RISC-V CPU. Add the tt-atlantis machine containing serial console, interrupt controllers, and device tree support. The Atlantis boot images loaded from include OpenSBI and an initial DTB that is passed to OpenSBI. This is approximated in the model by having QEMU build the device tree rather than load a DTB image directly. Subsequent stages may use the modified DTB provided by OpenSBI or opt to supply their own. qemu-system-riscv64 -M tt-atlantis -m 512M \ -kernel Image -initrd rootfs.cpio -nographic Co-Developed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260630024952.1520546-8-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/riscv/aia: Provide number of irq sourcesJoel Stanley
Instead of hard coding the number of IRQ sources used by the APLIC pass it in as a parameter. This allows other machines to configure this as required. The maximum number of sources is 1023. Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20260630024952.1520546-5-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/riscv/virt: Move AIA initialisation to helper fileJoel Stanley
The AIA init will be used by any server class riscv machine. Separate it out in order to share code with such systems. The virt machine keeps machine specific #defines such as VIRT_IRQCHIP_NUM_MSIS, VIRT_IRQCHIP_NUM_PRIO_BITS. Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20260630024952.1520546-4-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/riscv/boot: Account for discontiguous memory when loading firmwareNicholas Piggin
This loads firmware into the first (low) memory range, accounting for machines having discontiguous memory regions. Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20260630024952.1520546-3-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/riscv/boot: Describe discontiguous memory in boot_infoNicholas Piggin
Machines that have discontiguous memory may need to adjust where firmware and images are loaded at boot. Provide an interface for machines to describe a discontiguous low/high RAM scheme for this purpose. Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20260630024952.1520546-2-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/riscv: add create_fdt_plic() helperDaniel Henrique Barboza
Consolidate the common plic FDT code between 'virt' and sifive_u boards into a single place. Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260616235939.1358663-6-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/riscv/sifive_u: add #address-cells in PLIC FDTDaniel Henrique Barboza
By Linux FDT docs in [1] the "address-cells" property is mandatory. Set it to zero. While we're at it let's also put this new value and the interrupt-cells value in macros, like the 'virt' board is doing. [1] https://www.kernel.org/doc/Documentation/devicetree/bindings/interrupt-controller/sifive%2Cplic-1.0.0.txt Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260616235939.1358663-4-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/ufs: Populate cqe.task_tag for UFSHCI 4.1 tag decodingJeuk Kim
In UFSHCI 4.1 the MCQ completion queue entry carries the request tag in the cqe.task_tag field (DW5), whereas 4.0 hosts derive it from the UTP command descriptor base address. The device reports version 4.1 in the VER register but left task_tag/lun zero in the completion path, so a 4.1-compliant host reads tag 0 for every completion and cannot match it to the outstanding request. Add the task_tag/lun/iid fields to UfsCqEntry per the UFSHCI 4.1 CQE layout and populate them from the request UPIU header. For example, the Linux ufshcd_mcq_get_tag() uses cqe.task_tag for version >= 4.1, so without this SCSI commands hung (e.g. INQUIRY to the device W-LUN) while device-management commands still completed. Signed-off-by: Jeuk Kim <jeuk20.kim@samsung.com>
6 dayshw/ufs: Emulate DME_GET/SET for PA layer attributesJeuk Kim
After DME_LINK_STARTUP a UFSHCI host typically negotiates the link power mode: it reads PA layer attributes (connected RX/TX data lanes, max RX HS/PWM gears) via DME_GET and then issues DME_SET(PA_PWRMODE), waiting for the UIC power-mode-change completion (IS.UPMS / HCS.UPMCRS). The device only handled DME_LINK_STARTUP and DME_HIBER_{ENTER,EXIT} and returned FAILURE for every other DME command, so a host that performs power-mode change could never complete it. Return canned PA attribute values (1 lane, HS-G4, FAST_MODE) on DME_GET/PEER_GET and acknowledge DME_SET/PEER_SET. For DME_SET(PA_PWRMODE) also raise IS.UPMS and set HCS.UPMCRS=PWR_LOCAL so the power-mode change completes. The emulated link has no PHY, so no state is persisted. For example, the Linux ufshcd driver reads these attributes during probe and otherwise aborts with "invalid connected lanes value". Signed-off-by: Jeuk Kim <jeuk20.kim@samsung.com>
6 daysmigration: add migration_guest_ram_loading() helperDenis V. Lunev
Operations that read guest RAM (dump-guest-memory, memsave, pmemsave) must refuse to run while the destination of a migration is still receiving that RAM: during precopy it is incomplete, and during postcopy a read faults the page in from the source. Provide a single predicate they can share instead of open-coding the runstate and postcopy checks. Signed-off-by: Denis V. Lunev <den@openvz.org> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20260619101834.228432-2-den@openvz.org>
8 dayshw/hexagon: Define hexagon "virt" machineBrian Cain
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
8 dayshw/hexagon: Add machine configs for sysemuBrian Cain
Some header includes are modified here: these are uniquely required for basic system emulation functionality and had not been required for linux-user. Acked-by: Markus Armbruster <armbru@redhat.com> Co-authored-by: Mike Lambert <mlambert@quicinc.com> Co-authored-by: Sid Manning <sidneym@quicinc.com> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
8 dayshw/hexagon: Add globalreg modelBrian Cain
Some of the system registers are shared among all threads in the core. This object contains the representation and interface to the system registers. Reviewed-by: Sid Manning <sid.manning@oss.qualcomm.com> Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
8 dayshw/hexagon: Declare hexagon TLB device interfaceBrian Cain
Add the hexagon TLB device interface header. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
8 dayshw/arm: Plug FlexCAN into FSL_IMX6 and SabreliteMatyáš Bobek
FlexcanState is added to the FslIMX6State struct like other peripherals. Add two new machine properties to Sabrelite machine for linking the embedded FlexCAN instances to QEMU CAN buses by name. No other machine uses FslIMX6State. Signed-off-by: Matyáš Bobek <matyas.bobek@gmail.com> Signed-off-by: Pavel Pisa <pisa@fel.cvut.cz> Tested-by: Pavel Pisa <pisa@fel.cvut.cz> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Pavel Pisa <pisa@fel.cvut.cz> Message-id: 4159df998b0508bb411284ef406de23bbc5edfd8.1782140438.git.matyas.bobek@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 dayshw/net/can/flexcan: NXP FlexCAN core emulationMatyáš Bobek
Added the FlexCAN2 emulator implementation core, with CAN_FLEXCAN Kconfig flag and MAINTAINERS entry. FlexCAN2 version can be found in i.MX6 SoCs and others. More information about the implementation can be found in [1]. Some macro and struct defintions were borrowed from the Linux kernel. The original authors agreed with relicensing them to GPL-2.0-or-later on the qemu-devel mailing list. [1] http://dspace.cvut.cz/bitstream/handle/10467/122654/F3-BP-2025-Bobek-Matyas-BP_Bobek_FlexCAN_final_4.pdf Signed-off-by: Matyáš Bobek <matyas.bobek@gmail.com> Signed-off-by: Pavel Pisa <pisa@fel.cvut.cz> Tested-by: Pavel Pisa <pisa@fel.cvut.cz> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Pavel Pisa <pisa@fel.cvut.cz> Message-id: 03dc62ff8013bb946aab8f64e51638b810629529.1782140438.git.matyas.bobek@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 dayshw/misc/imx6_ccm: Add PLL3 and CAN clockMatyáš Bobek
Add fixed frequency (480 MHz) PLL3, of which the FlexCAN clock is derived, and compute FlexCAN frequency based on the divider configuration (CCM_CSCMR2). The clock frequency will be used for computing timestamps in FlexCAN emulator. Signed-off-by: Matyáš Bobek <matyas.bobek@gmail.com> Signed-off-by: Pavel Pisa <pisa@fel.cvut.cz> Tested-by: Pavel Pisa <pisa@fel.cvut.cz> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Pavel Pisa <pisa@fel.cvut.cz> Message-id: 95da33074f8b79842566d61e4e04448b1e622080.1782140438.git.matyas.bobek@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 dayshw/intc/gicv5: Define and use GICV5_PENDING_IRQ_NONEPeter Maydell
The GICv5PendingIrq struct representation of "there is no pending interrupt" sets the prio field to PRIO_IDLE, and generally to avoid confusion we also set the intid to 0. We want to return this value or initialize some variable to it in several places in the GICv5 implementation, and the support for the virtual interrupt domain introduces more. Define a convenience macro for this special-case struct value, and use it instead of opencoding either the structure initializer or explicit assignment to the two fields. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Message-id: 20260615105029.2898872-6-peter.maydell@linaro.org
9 daysMerge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi
* target/i386/mshv: CPU model support * target/i386/mshv: first part of migration support * target/i386/mshv: faster register access for MMIO exits * target/i386/tdx: add support for AMX alias bits in CPUID and AVX10 * Deprecate memory-encryption in favor of confidential-guest-support # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCgAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmo9sDwUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroOHBwf8Dx4gkbzOFxmCNX3EaW+ROYwlyAC7 # ADo9LFloDHXforRYTm4mBXNUVNF1/KFA6Tf92rzBlUZgp9KuMy/KhWZ1GbNsE+9b # k5/1RF9/IxRHy6GL69apdHEKY2OYzXl76or2HF3wMd6Mu77qD8Onthko81VaLWox # 5ZOBz6NaSnykzs9RimkVLtD9HswtFile2NWTPSliUV874lEJioNi9RcdhnQvJCnX # WqGWViC0THucIGCm+NVhSEmvRnAFbPgUBPvQuy7skLu+R7Ryy7GAWmE/gFlSrYy2 # 4c4zt4SB0tFYJlT9db5ZdaUSgCs52CFawQ9uTSEjNSmEEuQFzXGo6BeY4w== # =4V0w # -----END PGP SIGNATURE----- # gpg: Signature made Thu 25 Jun 2026 18:48:28 EDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (45 commits) i386/tdx: Add CPUID_24_0_EBX_AVX10_VL_MASK as supported i386/tdx: Make AMX alias bits supported i386/tdx: Use .has_gpa field to check if the gpa is valid machine: Deprecate memory-encryption qemu-options: Add description of tdx-guest object qemu-options: Add confidential-guest-support to machine options qemu-options: Change memory-encryption to confidential-guest-support in the example i386/sev: Remove the example that references memory-encryption target/i386/mshv: use the register page to set registers target/i386/mshv: use the register page to get registers target/i386/mshv: hv_vp_register_page setup for the vcpu include/hw/hyperv: add hv_vp_register_page struct definition accel: remove unnecessary #ifdefs target/i386/mshv: migrate CET/SS MSRs target/i386/mshv: migrate MTRR MSRs target/i386/mshv: migrate MSRs target/i386/mshv: reconstruct hflags after load target/i386/mshv: migrate XSAVE state target/i386/mshv: migrate pending ints/excs target/i386/mshv: move msr code to arch ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
11 daysinclude/hw/hyperv: add hv_vp_register_page struct definitionDoru Blânzeanu
Define the `hv_vp_register_page` structure that the linux kernel uses to allow access to vcpu registers. This structure is going to be used in later patches to access vcpu registers. Signed-off-by: Doru Blânzeanu <dblanzeanu@linux.microsoft.com> Reviewed-by: Mohamed Mediouni <mohamed@unpredictable.fr> Link: https://lore.kernel.org/r/20260428135053.251200-4-dblanzeanu@linux.microsoft.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
11 daystarget/i386/mshv: migrate CET/SS MSRsMagnus Kulke
This change migrates the MSRs required for CET shadow stack and indirect branch tracking. They are gated behind cet_ss_support || cet_ibt_support mshv processor feature flags. Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com> Link: https://lore.kernel.org/r/20260417105618.3621-24-magnuskulke@linux.microsoft.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
11 daystarget/i386/mshv: migrate MSRsMagnus Kulke
In this change the we rewrite the existing MSR logic to make MSRs migratable: - we map them on existing QEMU fields in the CPU. A table and a macro MSHV_ENV_FIELD is used to associate a HV register name to the their msr index and their offset in the cpu state struct. The list is not exhaustive and will be extended in follow-up commits. - mshv_set/get_msrs() fns are called in the arch_load/store_vcpu_state() fns. they use use generic registers ioctl's and map the input/output via load/store_to/from_env() from/to the hv register content to the cpu state representation. - init_msrs() has been moved from mshv-vcpu to the msr source file - we need to perform some filtering of MSR because before writing and reading, because the hvcalls will fail if the partition doesn't support a given MSRs. - Some MSRs are partition-wide and so we will only write the to on the BSP. Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com> Link: https://lore.kernel.org/r/20260417105618.3621-21-magnuskulke@linux.microsoft.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
11 daysMerge tag 'ui-pr-v1' of https://gitlab.com/marcandre.lureau/qemu into stagingStefan Hajnoczi
UI patches - ui: better console hotplug support - vga: implement blinking To: qemu-devel@nongnu.org Cc: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEh6m9kz+HxgbSdvYt2ujhCXWWnOUFAmo7wlsACgkQ2ujhCXWW # nOUAaA/+OWDMM1SdVCk9M9K/sWiSP2fsXAB+Zpdj9mUKz4B86ulVAc5Wv0ROMKyC # hO9XT8ksCC5Xuehhfb1gxhazA46z9QWDiZ1Drnm945WUJF9U6zcqMS9w343HNL/p # HE+wCxz+D2Izx0wrlPHVPnNp+54Ge/YK4vNjfGKSXdwFGgQPfqMX3D+chL57/quG # xttjbDNixplqxKGqzmQRIZKgifyrMUs1knLv+bi7BHGnKIws1ww5EwOAF9zfY626 # ouo5knVNqRKMekCudIudWIYKNtVSV2WPQz/k2AdNq5L0NeI2Mj6tFswVSfLlZ1LZ # Np0Ijeip2EOYLuPTZJKZmAWlsUK1E/VXqpehzmZdi07i37kHJBafppPOD2//P3Bs # UB8pXVcjlXrHxEwkwEKRLHsAbivmD/bszLeNj+/E1V9M7P9pIc0jiEYPG+9WniYv # CJZ9w9Q9S7C1IKjRIRtR/veLI4MxBu/gz5DG8qzD2GfRVpGUV8J5loSc2CidBvCR # Vk7fetkBLh9vWgWqqbBBguHieiqoWqJZ3OL+F+tMRfiA7WIJgl2K6hRlmA5baQpW # pD794a2bn6h6jK26natfdA6Ns4NfWc4R/3lZRNqX3cPjyAy98nxdmCQwDJBV61e9 # e9YKU2tJ6zruUs3Oa9/XW/W4kyEm+aBXdysg5KziXUKLx3pHTOY= # =N7bZ # -----END PGP SIGNATURE----- # gpg: Signature made Wed 24 Jun 2026 07:41:15 EDT # gpg: using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5 # gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [full] # gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [full] # Primary key fingerprint: 87A9 BD93 3F87 C606 D276 F62D DAE8 E109 7596 9CE5 * tag 'ui-pr-v1' of https://gitlab.com/marcandre.lureau/qemu: (35 commits) vga: implement text mode character blink tests/qtest: add D-Bus display hotplug test ui/dbus: handle console hotplug/unplug events ui/console: unregister console from QOM tree on close ui/console: register console in QOM tree dynamically ui/gtk: handle console hotplug/unplug events ui/gtk: centralize console menu and shortcut management ui/gtk: fix tab re-insertion order on window close ui/gtk: move global display settings out of per-console init ui/gtk: convert VirtualConsole storage from fixed array to GPtrArray ui/console-vc: fire ADDED/REMOVED notifications ui/console: fire console ADDED/REMOVED notifications ui/console: add console event notifier infrastructure ui/gtk: implement display cleanup ui/dbus: implement display cleanup ui/cocoa: implement display cleanup ui/egl: implement display and EGL cleanup ui/spice-app: implement display cleanup ui/sdl2: implement display cleanup ui/curses: implement display cleanup ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
11 daystarget/i386/mshv: migrate pending ints/excsMagnus Kulke
We use PENDING_INTERRUPTION, INTERRUPT_STATE, PENDING_EVENT hv registers to map and roundtrip from/to CPUX86State. We ignore HV_REGISTER_PENDING_EVENT1 which represent events for nested virt contexts, as we don't support nested virt with MSHV currently. Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com> Link: https://lore.kernel.org/r/20260417105618.3621-30-magnuskulke@linux.microsoft.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
11 daysaccel/mshv: enable dirty page trackingMagnus Kulke
This change introduces the functions required to perform dirty page tracking to speed up migrations. We are using the sync, global_start, and global_stop hooks. The sync is implemented in batches. Before we can disable the dirty page tracking we have to set all dirty bits. Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com> Link: https://lore.kernel.org/r/20260417105618.3621-35-magnuskulke@linux.microsoft.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
11 daystarget/i386/mshv: expose mshv_get_generic_regsMagnus Kulke
We expose the fn, so we can call them from the other source files (msr.c). Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com> Link: https://lore.kernel.org/r/20260417105618.3621-20-magnuskulke@linux.microsoft.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
11 daysaccel/mshv: store partition proc featuresMagnus Kulke
We retrieve and store processor features on the state, so we can query them later when deciding which MSRs to migrate. Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com> Link: https://lore.kernel.org/r/20260417105618.3621-19-magnuskulke@linux.microsoft.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
11 daysaccel/mshv: remove redundant msi controllerMagnus Kulke
The remaining MsiControl infrastructure can be removed now Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com> Link: https://lore.kernel.org/r/20260417105618.3621-14-magnuskulke@linux.microsoft.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
11 daysaccel/mshv: reserve ioapic routes on s->irq_routesMagnus Kulke
We reserve 24 ioapic routes using the new functions that operate on the mshv apic state. commit/add_msi_routing() fn's can be removed now. Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com> Link: https://lore.kernel.org/r/20260417105618.3621-13-magnuskulke@linux.microsoft.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
11 daysaccel/mshv: use s->irq_routes in commit_routesMagnus Kulke
In mshv_irqchip_commit_routes() the entries that have been accumulated in s->irq_routes are committed directly to MSHV's irqchip. The old commit_msi_routing_table() fn will be removed in a subsquent commit. Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com> Link: https://lore.kernel.org/r/20260417105618.3621-12-magnuskulke@linux.microsoft.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
11 daysaccel/mshv: update s->irq_routes in release_virqMagnus Kulke
The state's irq_routes field will be updated when an irqchip's gsi is requested to be released. The old remove_msi_routing() fn is redundant and can be removed. Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com> Link: https://lore.kernel.org/r/20260417105618.3621-11-magnuskulke@linux.microsoft.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
11 daysaccel/mshv: update s->irq_routes in add_msi_routeMagnus Kulke
The irq_routes field of the state is populated with native mshv irq route entries. The allocation logic is modelled after the KVM implementation: we will always allocate a minumum of 64 entries and use a bitmask to find/set/clear GSIs. The old implementation of add_msi_routes will be removed in a subsequent commit. Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com> Link: https://lore.kernel.org/r/20260417105618.3621-9-magnuskulke@linux.microsoft.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
11 daysaccel/mshv: add irq_routes to stateMagnus Kulke
This change adds fields related to irq routing to the MSHV state, following similar fields in the KVM implementation. So far the fields are only initialized, they will be used in subsequent commits for bookkeeping purposes and storing uncommitted interrupt routes. The TYPE_MSHV_ACCEL defines have been moved to the header. Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com> Link: https://lore.kernel.org/r/20260417105618.3621-8-magnuskulke@linux.microsoft.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
11 daysaccel/accel-irq: add generic commit_route_changesMagnus Kulke
A generic accel_irqchip_commit_route_changes() fn has been introduced for usage in the MSHV accelerator. The respective kvm_ fn can be removed since we handle the commit op in a generic way. Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com> Link: https://lore.kernel.org/r/20260417105618.3621-7-magnuskulke@linux.microsoft.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
11 daysaccel/accel-irq: add generic begin_route_changesMagnus Kulke
A generic accel_irqchip_begin_route_change() fn has been introduced for usage in the MSHV accelerator. It replaces the respective kvm_ fn. Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com> Link: https://lore.kernel.org/r/20260417105618.3621-6-magnuskulke@linux.microsoft.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
11 daysaccel/accel-irq: add AccelRouteChange abstractionMagnus Kulke
The accelerated irqchip routines use a record of changes to batch changes when programming routes. Currently this mechanism is coupled to the KVM accelerator, this change introduces an abstraction that replaces KVMRouteChange and keeps a pointer to an abstract AccelState instead of the concrete type, converting the state where necessary. This is done to further align the irqchip programming in the MSHV accelerator with the existing KVM code in QEMU. Subsequent commits will introduce AccelRouteChange to the MSHV accelerator code. Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com> Link: https://lore.kernel.org/r/20260417105618.3621-5-magnuskulke@linux.microsoft.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
generated by cgit v1.2.3 (git 2.39.1) at 2026-07-07 03:09:27 +0000