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43 hoursMerge tag 'firmware-20260704-pull-request' of https://gitlab.com/kraxel/qemu ↵HEADmasterStefan Hajnoczi
into staging igvm: add device tree support # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEoDKM/7k6F6eZAf59TLbY7tPocTgFAmpIkaMACgkQTLbY7tPo # cTg4NA/8CB9HEZG6kKV1fh/7N5ev0iL5S1K3HCxKYcHoyMfkkhDvORSa5oF8gYoP # HiJC4D+8X+523YFOzvxsaRgTC0J6iRucktIz2PNHBpy7npcQpiRjI1l9Z4FPEH0b # iPSuKgpliOYIUi/ckeTKK4q2GwYsxIaLhu/uGsEr10cCf62JkXigkc5t1ZXa/ggv # HYBVNE9HM6CG6SWQKEqrfuSYex8Xa4+x/euzsAgDkuEBfYykHt4duDD1iObEJ6Cy # 3UXodgkcLrnz5baWbtTNjmVRsQfyjtD7/kfo4yPNvzC80UIjdvxg4COXF6YxId5P # gDBWl8bY9rqYah8zQ4QzxbVZ7HWJDCILLWc0O2Mlw70KdUQ7g5JA1Gjf6Ms5YgB6 # PEH+rJ9ir09MJ9Z7AWRo3Ry91opDGrKUos2maQHdf8AADV9afmJVQ1frnDgUjF/3 # PXZVVCSpVoLBP5GLT+2l60qFYzJPqd/HsK5cWGaZEJyfvejrZjEVI6l9FliQFJ9l # HiLEo2yhWVtRzruy7Uv16tU42xODmDMBKU12HZfQLvYbKUaBf24YpLiBprEzUM72 # snXGhZX7wQl6ghQ7mxdLncECRRvFwuknZPeLBPWyp6rm5IuTvxkhRtgCHS4RFYbr # 7NDjzJ3/gg9YXy3z0cJjRkaBfJvwdYTUTpuq0yDVOfNL53L0jbA= # =7c95 # -----END PGP SIGNATURE----- # gpg: Signature made Sat 04 Jul 2026 06:52:51 CEST # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * tag 'firmware-20260704-pull-request' of https://gitlab.com/kraxel/qemu: igvm: add device tree parameter support igvm: use idiomatic meson conditional for IGVM build files igvm: Report error on missing parameter area in directive handlers Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
43 hoursMerge tag 'pull-ppc-for-11.1-misc-20260703' of ↵Stefan Hajnoczi
https://gitlab.com/harshpb/qemu into staging PPC queue for 2026-07-03 # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEa4EM1tK+EPOIPSFCRUTplPnWj7sFAmpHPNAACgkQRUTplPnW # j7tkjQ/9FP3/sTw0MxhGdLItxurrEzu3f4jiDKpnjEIqiJInzYl/2fJKZU611PSp # gydfdNhkr71TxuJggibAosEblcWRq9KqQXysDpNrJ8rqEIeLj0lv9/JigLTZqU3e # vsfDmfdCAB7YTtpm6HkTYW81EPD0X8AwQqz4FCNDQ0zeNUBIU8IU/ARP2j80CTnm # 5xRK42aZb9CMYYIk3p8l4FuZmv6Y0Jf0daXM4WsEdHu9KjGvYr1glTY/lgblNPug # kWIcjPqQ6x/hloYqxTTcsfJBnKfdaVppuh6LbJbgISsQIBzTqrD2HvEIpNFJRKnS # 1XGwLj6cMmm4u2tv3BF0yVDJCEff312n2VFskmOrCUJOR+g2UqDzMb4+7JOpufEn # Fla38+a9H9ThdnUNaak8+KquHDOJzDAOugOdMvsID8KlJ/q3wrTTEUUImj5Bwyqz # Gc7naNx+3D+BSiahDe4LP71ZFLrQJ/eYCj71for5xZNcZVOQ6IDhymEMUAcRzkt6 # 2qICF6XmkYfuH+1113KMxG65NpKGEvktONQ6UpLWTubQ++BNK1Bt2v8PAWSis/d8 # EYg5M/R7RqhbxufIUDLXJIuxB3xuiVg+e+x/M8X0LffmYhPI1cuZPmth4/75IKL+ # 9Vddgc1hSHX1EUjRyZpoK6WArOTNvUOZMEcAhGr/0NgK5O/1Z10= # =1TRv # -----END PGP SIGNATURE----- # gpg: Signature made Fri 03 Jul 2026 06:38:40 CEST # gpg: using RSA key 6B810CD6D2BE10F3883D21424544E994F9D68FBB # gpg: Good signature from "Harsh Prateek Bora <harsh.prateek.bora@gmail.com>" [full] # gpg: aka "Harsh Prateek Bora <harshpb@linux.ibm.com>" [full] # Primary key fingerprint: 6B81 0CD6 D2BE 10F3 883D 2142 4544 E994 F9D6 8FBB * tag 'pull-ppc-for-11.1-misc-20260703' of https://gitlab.com/harshpb/qemu: ppc/pnv: add test to verify external DTB is honored ppc/pnv: avoid regenerating DTB if external DTB is present docs/system/ppc/pseries: Update the link to the SLOF repository target/ppc: Expose the TB offset of the guest in QEMU monitor hw/pci-host: Split PowerNV PHB5 code from PHB4 files Revert "hw/ppc: Deprecate 405 CPUs" pseries: Update SLOF firmware image to release 20260627 Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
4 daysMerge tag 'pull-qobject-2026-07-02' of https://repo.or.cz/qemu/armbru into ↵Stefan Hajnoczi
staging QObject patches for 2026-07-02 # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCgAwFiEENUvIs9frKmtoZ05fOHC0AOuRhlMFAmpGUpgSHGFybWJydUBy # ZWRoYXQuY29tAAoJEDhwtADrkYZTA3wP/jXwy30ND7OQE5HErDKp4priCm9cMPcR # 30FxOS+E9bAT6KCDmnUqRVELebGn0x3gz9MXWO8qQcU4MHneN4M/42Dh/oa1t+xd # Zva2rIfVW1FHPvzEfsKsUFPq1LaY+uM9XW2DdEjyv11RoMZwVHiWseURXwB2HNLH # HNfxBOlGa8VTvI5kpRafN+DNRjeMEWcIXqZRHr51GeFfc6av0CTUYM2xdwRQTw3m # GQGDvLIllxb9STwnSKieBdkCpBGSwffcjJipt7VmvORYNsi3pcJgAhWFzM9UWqPp # ZENwziphyd/4XLAC4EaMlXnXlAzLJh+H7+th6Ylirkjo1sULO9cCFbYcANqljLdT # GIIafRoe4zuZp1gFPgT51nA53Adzd1TWCT462R1uzbVJxoEdthsYVB7WMamBJySA # MuuMjq4JVeROBgDbO/X7+EnzmI0torT24XpFxFjfBGb9zSnG7YRzSSf8sDQIwir+ # tlh0e6LzsVJckJ0IUAjglLKb49QUnmzrSx8+6LCH0iFMkHWwXdtd5Vyk5SofIXIy # Dc6t2qH8USkOjwgs5vKdr9m8LEv2iELegpanmZDTd+zIEFR1WP1SRiirmkoD7QJY # 0zK3gabC5uUpcfKx6EE2UXWpFW/tVDjMUN43QoL48/pVDuYUcqXJ8y2DEqjHV4Sd # O5wd3ZOFdvVc # =jshD # -----END PGP SIGNATURE----- # gpg: Signature made Thu 02 Jul 2026 13:59:20 CEST # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * tag 'pull-qobject-2026-07-02' of https://repo.or.cz/qemu/armbru: json-parser: add location to JSON parsing errors json-streamer: do not heap-allocate JSONToken json-streamer: remove token queue json-streamer: make brace/bracket count unsigned json-streamer: reuse parser json-parser: replace with a push parser qobject/json-writer: preallocate output buffer Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
4 daysppc/pnv: add test to verify external DTB is honoredShivang Upadhyay
Test boots a powernv11 machine, using a custom dtb. Custom dtb has the following bootargs. chosen { bootargs = "hello world"; }; Test Checks whether above bootargs make it to kernel's command line. Reviewed-by: Aditya Gupta <adityag@linux.ibm.com> Signed-off-by: Shivang Upadhyay <shivangu@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260630103508.254000-3-shivangu@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
4 daysppc/pnv: avoid regenerating DTB if external DTB is presentShivang Upadhyay
Currently externally provided dtb is overwritten in `pnv_reset`. Fix this by only creating dtb if not provided from `-dtb`. Reviewed-by: Aditya Gupta <adityag@linux.ibm.com> Signed-off-by: Shivang Upadhyay <shivangu@linux.ibm.com> Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260630103508.254000-2-shivangu@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
4 daysdocs/system/ppc/pseries: Update the link to the SLOF repositoryThomas Huth
SLOF has been moved to gitlab.com already a while ago. We updated the link in pc-bios/README in commit 7f98b4f25ed9 ("pseries: Update SLOF firmware image"), but forgot to update it in the manual, too. Signed-off-by: Thomas Huth <th.huth@posteo.eu> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260702074842.4806-1-th.huth@posteo.eu Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
4 daystarget/ppc: Expose the TB offset of the guest in QEMU monitorGautam Menghani
When debugging issues in KVM guests, it is sometimes helpful to have a unified trace log of both guest and host to see where things are going wrong. Expose the TB (timebase) offset through QEMU monitor to enable capturing of unified log. The below steps can be then used for KVM guests to get a unified log: 1. In host trace-cmd record -e kvm_hv:kvm_guest_enter -e kvm_hv:kvm_guest_exit \ -C ppc-tb -o trace_host.dat 2. In guest trace-cmd record -e powerpc:hcall_entry -e powerpc:hcall_exit -C ppc-tb \ --ts-offset <TB offset from QEMU monitor> -o trace_guest.dat NOTE: The TB offset would be reported as a negative number in QEMU monitor. For this step, the minus sign must be ignored. 3. Transfer the guest logs to the host with scp/rsync 4. Unify the logs trace-cmd report -i trace_host.dat -i trace_guest.dat > combined_log In case of TCG guests, the TB offset would be reported as 0 since the offset logic is not applicable in this case. Tested-by: Amit Machhiwal <amachhiw@linux.ibm.com> Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com> Reviewed-by: Vaibhav Jain <vaibhav@linux.ibm.com> Signed-off-by: Gautam Menghani <gautam@linux.ibm.com> Tested-by: Sneh Shikha Yadav <syadav@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260629052602.78276-1-gautam@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
4 dayshw/pci-host: Split PowerNV PHB5 code from PHB4 filesJishnu Warrier
Separate Power10/11 PHB5 implementation from Power9 PHB4 code for better maintainability and clarity. This is a pure code movement with no functional changes. Signed-off-by: Jishnu Warrier <jishnuvw@linux.ibm.com> Reviewed-by: Aditya Gupta <adityag@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260608093430.2729688-1-jishnuvw@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
4 daysRevert "hw/ppc: Deprecate 405 CPUs"Glenn Miles
This reverts commit 52f0b59ec6b780f2a3e162d5862b90b406fa4697. The PowerPC 405 CPU is used by the PPE42 CPU which was added to QEMU v10.2. The PPE42 CPU is basically a stripped down version of the PowerPC 405 CPU and is used by the Power9, Power10, and Power11 CPUs as an embedded processor to handle various tasks. Also, IBM has plans to use the PowerPC 405 CPU model within a year to model the On Chip Controller (OCC), which has an embedded PPC405 CPU. Therefore, this patch removes the PowerPC 405 CPU from the deprecated list. Signed-off-by: Glenn Miles <milesg@linux.ibm.com> Acked-by: Cédric Le Goater <clg@redhat.com> Acked-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260505144621.1308457-1-milesg@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
4 dayspseries: Update SLOF firmware image to release 20260627Thomas Huth
Contains a fix for the parsing of ELF program headers. Signed-off-by: Thomas Huth <th.huth@posteo.eu> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
4 daysMerge tag 'dump-pr-v1' of https://gitlab.com/marcandre.lureau/qemu into stagingStefan Hajnoczi
Dump patches for 2026-06-30 To: qemu-devel@nongnu.org Cc: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEh6m9kz+HxgbSdvYt2ujhCXWWnOUFAmpD3PsACgkQ2ujhCXWW # nOUW8g//W75y5yaaujNXQ/tqRmIGpVKuB1rC5QXJgRYQlpEIh21tPeHHUUFpOSgU # llgo2NZM4fqX450vBDU2L6J+qtGc7Q6tm3EKlAe+dZeIlqCcrvHDTGHLq83pCGZQ # LbABgwnxRcK+BOmSH/LdsP33dFYWBMMwSNZ0P/C986pAs5m/Ji6oz7OI1hRvv5E/ # /HjwJLaXbCyOesWicKpFmN2wiwi3GRiiwI5mBBrue3mmkTvHzb52Pas/B+jT/q/G # WzIKMYUAwlvYIg2NiWcr1r5UAaXohq4Z4O8jWSpXFoZbg24B5GfmPzg2/mWKtFs1 # UN5J5soqHA/7DV+hDK6v3dPWFnjAMe5PtxjtFdxlt7z5B0LS2hnwHW3tbZtWIhbV # cFUheXb+ySVw6h0ieK/Ym5k76tExvWHMDfacBHD6oo+ikiOxifCdSSvADYYvnpIU # ySfjfnEwXg2F/TrsL1o4uotcHeyONJEjy/V6l+pgOATyTGfUvUk0PCRwGNNBhshx # fZVbP8TSFw3NmS5j86dPUa8hyX1AZPRwSnxPzN/iOnCGigyPjJ3clcGQZ1YGwnip # KvDXQjmoirJutwEWVd1HZmGnWUqAfrJuselSvER5dWFEKnukbn7wmkIQx3aixZT4 # 1/AUNqPsMNREDTMHN6KCAK7mj7024Gq2Gmupu7aYpdZZtPHUXPA= # =NMTJ # -----END PGP SIGNATURE----- # gpg: Signature made Tue 30 Jun 2026 17:12:59 CEST # gpg: using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5 # gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [full] # gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [full] # Primary key fingerprint: 87A9 BD93 3F87 C606 D276 F62D DAE8 E109 7596 9CE5 * tag 'dump-pr-v1' of https://gitlab.com/marcandre.lureau/qemu: dump: fix misleading VMCOREINFO phys_base parse error tests/qtest/dump: cover win-dmp availability via vmcoreinfo tests/qtest/dump: reject win-dmp without vmcoreinfo tests/qtest: add dump-guest-memory test dump: make win_dump_available() check vmcoreinfo for a Windows dump header system/cpus: refuse memsave/pmemsave while guest RAM is being migrated dump: refuse dump-guest-memory while guest RAM is being migrated migration: add migration_guest_ram_loading() helper Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
5 daysjson-parser: add location to JSON parsing errorsPaolo Bonzini
Now that all calls to parse_error have a token, add the line and column to the message. As far as I can see the two important TODOs (better errors and better EOI handling) are done, and the others (token range information and "parsed size"?) do not really matter or are handled better by json-streamer.c. So remove the list, which had sat unchanged since 2009. This needs some adjustments to provide a good x and y for error messages. First of all, they switch from zero-based to one-based, which is safe because they were both sitting unused. Second, right now the x and y are those of the *last* character in the token. Modify json-lexer.c to freeze tok->x and tok->y at the first character added to the GString. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20260626101727.1727389-7-pbonzini@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
5 daysjson-streamer: do not heap-allocate JSONTokenPaolo Bonzini
This is not needed with a push parser. Since it processes tokens immediately, the JSONToken can be created directly on the stack and does not need to copy the lexer's string data. Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20260626101727.1727389-6-pbonzini@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
5 daysjson-streamer: remove token queuePaolo Bonzini
Now fully exploit the push parser, feeding it one token at a time without having to wait until braces and brackets are balanced. While the nesting counts are retained for error recovery purposes, the system can now report the first parsing error without waiting for parentheses to be balanced. This also means that JSON_ERROR can be handled in json-parser.c, not json-streamer.c. After reporting the error, json-streamer.c then enters an error recovery mode where subsequent errors are suppressed. This mimics the previous error reporting behavior, but it provides prompt feedback on parsing errors. As an example, here is an example interaction with qemu-ga. BEFORE (error reported only once braces are balanced): >> {"execute":foo >> } << {"error": {"class": "GenericError", "desc": "JSON parse error, invalid keyword 'foo'"}} >> {"execute":"somecommand"} << {"error": {"class": "CommandNotFound", "desc": "The command somecommand has not been found"}} AFTER (error reported immediately, but similar error recovery as before): >> {"execute":foo << {"error": {"class": "GenericError", "desc": "JSON parse error, invalid keyword 'foo'"}} >> } >> {"execute":"somecommand"} << {"error": {"class": "CommandNotFound", "desc": "The command somecommand has not been found"}} Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20260626101727.1727389-5-pbonzini@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> [Token size limit check off-by-one fixed] Signed-off-by: Markus Armbruster <armbru@redhat.com>
5 daysjson-streamer: make brace/bracket count unsignedPaolo Bonzini
It makes no sense to let brace_count and bracket_count go negative, also because it immediately ends error recovery and sets them both back to zero. Instead set them to zero *before* choosing whether to process the token queue; this makes it possible to have the fields as unsigned. Note that JSON_END_OF_INPUT now forces the parentheses to appear balanced, so that the queue is emptied and an error is reported; hence, the "type != JSON_END_OF_INPUT" condition can be removed. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20260626101727.1727389-4-pbonzini@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> [Comment tweaked] Signed-off-by: Markus Armbruster <armbru@redhat.com>
5 daysjson-streamer: reuse parserPaolo Bonzini
The push parser can be reset, so reuse it when the json-streamer detects a completed toplevel object. Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20260626101727.1727389-3-pbonzini@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
5 daysjson-parser: replace with a push parserPaolo Bonzini
In order to avoid stashing all the tokens corresponding to a JSON value, embed the parsing stack and state machine in JSONParser. This is more efficient and allows for more prompt error recovery; it also does not make the code substantially larger than the current recursive descent parser, though the state machine is probably a bit harder to follow. The stack consists of QLists and QDicts corresponding to open brackets and braces, plus optionally a QString with the current key on top of each QDict. After each value is parsed, it is added to the top array or dictionary or, if the stack is empty, json_parser_feed returns the complete QObject. For now, json-streamer.c keeps tracking the tokens up until braces and brackets are balanced, and then shoves the whole queue of tokens into the push parser. The only logic change is that JSON_END_OF_INPUT always triggers the emptying of the queue; the parser takes notice and checks that there is nothing on the stack. Not using brace_count and bracket_count for this is the first step towards improved separation of concerns between json-parser.c and json-streamer.c. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20260626101727.1727389-2-pbonzini@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> [Minor comment improvements] Signed-off-by: Markus Armbruster <armbru@redhat.com>
5 daysqobject/json-writer: preallocate output bufferBin Guo
json_writer_new() creates the output GString with g_string_new(NULL), which starts at the GLib default of 64 bytes. Serializing typical QMP responses then requires multiple reallocations as the buffer grows -- for query-qmp-schema the GString is reallocated 12+ times. Preallocate JSON_WRITER_INITIAL_SIZE (4096) bytes. This covers most QMP responses without any reallocation. The JSONWriter is a short-lived object so the preallocation does not accumulate. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Bin Guo <guobin@linux.alibaba.com> Message-ID: <20260603022538.92780-1-guobin@linux.alibaba.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
5 daysigvm: add device tree parameter supportLuigi Leonardi
Coconut SVSM, with the upcoming device tree support [1], will use the IGVM device tree parameter to discover virtio-mmio and ISA serial devices instead of relying on the fw_cfg interface, which is QEMU-specific. The device tree is packed before copying into the IGVM parameter area to reduce its size, since IGVM files can define tighter memory constraints for parameter areas. Packing is done in the generic IGVM backend rather than in per-architecture device tree setup code, so that each architecture does not need to handle it individually. [1] https://github.com/coconut-svsm/svsm/pull/1006 Signed-off-by: Luigi Leonardi <leonardi@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Message-ID: <20260626-microvm_device_tree-v6-3-9cd13cf057e2@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
5 daysigvm: use idiomatic meson conditional for IGVM build filesLuigi Leonardi
Replace the explicit igvm.found() check with system_ss.add(when:, if_true:), matching the pattern used by all other optional backends. Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Luigi Leonardi <leonardi@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Message-ID: <20260626-microvm_device_tree-v6-2-9cd13cf057e2@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
5 daysigvm: Report error on missing parameter area in directive handlersLuigi Leonardi
Parameter areas are how an IGVM file tells QEMU to allocate buffers for runtime information the guest needs — VP count, memory map, MADT and so on. Usage directives reference a parameter area by index to tell QEMU where to write each piece of data. If the index doesn't match any declared parameter area, the data has nowhere to go and should be treated as an error. The directive handlers that look up a parameter area all return 0 (success) when `qigvm_find_param_entry()` can't find it. Therefore, the load succeeds but the guest never gets the expected parameters. Note that the IGVM library already validates parameter area indices when the file is loaded, so this path should only be reachable with a malformed file that bypassed library validation. This is defensive programming against that case. Report the error with error_setg() and return -1 instead. Signed-off-by: Luigi Leonardi <leonardi@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Message-ID: <20260626-microvm_device_tree-v6-1-9cd13cf057e2@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
5 daysMerge tag 'pull-riscv-to-apply-20260701' of ↵Stefan Hajnoczi
https://github.com/alistair23/qemu into staging RISC-V PR for 11.1 * Fix IMSIC CSR write and add tests * Parametrise debug trigger number * Add 'svbare' satp-mode * Fix RINTC PLIC context ID for KVM * Avoid abort when reading vtype before env->xl is set * Skip reset for KVM irqchip * Skip FP/Vector sync on KVM_PUT_RUNTIME_STATE * More FDT cleanups (PLIC) * Make FCTL.BE in IOMMU read only 0 * Check DC.TC reserved bits in IOMMU * Apply UXL WARL handling to vsstatus * Set cmd_ill IOFENCE.C if rsvp bits are set in IOMMU * Set RISCV_IOMMU_FQ_HDR_PV appropriately * Fix MSI MRIF IOMMU interrupt-pending offset * Report QEMU CPU archid as 42 * Check PMP before updating PTE * Add the Tenstorrent Atlantis machine # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmpE6SoACgkQr3yVEwxT # gBOxNQ//bI4BvnT65Kd2UNMgtAwwPPcehpsyPzC2S3BcflniXQL+fV6sQ7IreKta # 6dclp/v5v+yhbB4bd/E1s/UPOF3YD4A9noUFifIhymBkafmqA4YRNsvPByeGiSD8 # xVkHhX5qUT9NW5wKnivEDjO8mndBMRm5YEXQ6uT5ulUsZr3Ir8wPOCJITZ8ZqKwb # 6dbbXStf1aTIBzu53KaNhNpi9DQqKV5UeV7CiSuhuwWU0qmVg1RAZMg9X3oB80rE # WpWqH0rg9Z0Cn+3XL+oKSzbLD5SrrTV+Ohq+K8zT2rEk+hIXOE3shAPm2xfTT9Q2 # g65nBOf2UmNWeHlvn3XC2LtmIWq10/A78ogGgm4XwHx8TXIeA2KIKboyS8T37XAb # NwUllq9LRtfDVtDevpiTn6t7Oa7TC8zrxDJTT1rg/p+3D6MdfkonifwJJgVAwfuG # NF7R2iePKPQliWr1hi6W+ghzQMRFXgNBwUNOL39/BQguy5IqvNmSk6ovhl8IFocf # aXGh9U35DqgrsUvMa/7Fgf4uI2QNhERBGJrHfL0SPZ82sKb5CTrMw9URwg0DFnEF # 8v/zQ9xL4eF0uZn0OtaNlLXRCblDxcHSgecwix9Vip5toFIc1P8ar9FX98Zd/H5l # UD/a3ENtiwb6hnKhZ+45iM/NIFJeUK7A0944VnQzx00tA06wJLw= # =a4hl # -----END PGP SIGNATURE----- # gpg: Signature made Wed 01 Jul 2026 12:17:14 CEST # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20260701' of https://github.com/alistair23/qemu: (39 commits) hw/riscv/riscv-iommu.c: always fault with SADE=0 and A=0 hw/riscv/atlantis: Add some i2c peripherals hw/riscv/atlantis: Integrate i2c controllers hw/i2c: Add DesignWare I2C Controller tests/functional/riscv64: Add tt-atlantis tests hw/riscv/atlantis: Ensure OpenSBI has a non-zero next_addr hw/riscv: Add Tenstorrent Atlantis machine target/riscv: tt-ascalon: Enable Zkr extension hw/riscv/aia: Configure stride for the M-mode IMSIC hw/riscv/aia: Provide number of irq sources hw/riscv/virt: Move AIA initialisation to helper file hw/riscv/boot: Account for discontiguous memory when loading firmware hw/riscv/boot: Describe discontiguous memory in boot_info target/riscv: Check PMP before updating PTE target/riscv: Report QEMU CPU archid as 42 hw/riscv/riscv-iommu.c: fix MSI MRIF interrupt-pending offset hw/riscv/riscv-iommu.c: set RISCV_IOMMU_FQ_HDR_PV appropriately hw/riscv/riscv-iommu: set cmd_ill IOFENCE.C rsvp bits are set target/riscv: Apply UXL WARL handling to vsstatus hw/riscv/riscv-iommu: check DC.TC reserved bits ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
5 daysMerge tag 'pull-ufs-20260701' of https://gitlab.com/jeuk20.kim/qemu into stagingStefan Hajnoczi
ufs queue # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEUBfYMVl8eKPZB+73EuIgTA5dtgIFAmpEoa0ACgkQEuIgTA5d # tgLm1Q//Vqj6g2tNoiGqfIhuuUGjYiMifyfRzF9ZGVKBUwXeduaJ0gXE05duVbCx # FZyheWVUzvovDyWMgvpk0NwBz0WIEUWmWj9GtKnGMpRU9cFxATlUuFbYU+tY2aZC # dt6Ck3saRrVDvcrETucgkzL8HuEehXtZCfnqNmEkggXuhuaPJnkm8bKzs5fxapF/ # QT4T1j2RTFkWtHTfvnXrQiDmqVTGpRlI2USjCdCd3RUFxnKbFZJ8EcLJVAYPGrBR # RRi2eY4M2hCbZnNctpYfj86GltbFypnPfuhT+HVbIsue9+FEWScTa7BGeWpZETjJ # Drj19XAWbponVYXya57Me7I83b3+UJjSQe2eH4OGB0iTeqAlTQggAkmofzHWqD50 # +OyY6zT0TkPDpLmcBUbIwk94A+qV9iVETOLc0W2jX5CYrawD+lI9tAKeGtO6lv8c # Os5dy1vHvulDhd8H4tuCyepwLmU8KETZMDbSRwyQfgBKJx1eknqY0ITKynXbalIr # y1y5SzW+KnvB/2Dap3wfbYxpT441PEMlpN9cQslEALP+oHg80g+DdR47VJVJIkPM # 4ZR9T8LN8bm0hyzGVooQ0VpeKTA5ualAr9f0kT40a/8MuhedsXSy9XQBe9PYTiOe # 3MHqqPQFmwOXH6dzMUV44r0K9mW0QheBC9gLywq1yy4EIJ5DWMs= # =pbB1 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 01 Jul 2026 07:12:13 CEST # gpg: using RSA key 5017D831597C78A3D907EEF712E2204C0E5DB602 # gpg: Good signature from "Jeuk Kim <jeuk20.kim@samsung.com>" [unknown] # gpg: aka "Jeuk Kim <jeuk20.kim@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 5017 D831 597C 78A3 D907 EEF7 12E2 204C 0E5D B602 * tag 'pull-ufs-20260701' of https://gitlab.com/jeuk20.kim/qemu: hw/ufs: Populate cqe.task_tag for UFSHCI 4.1 tag decoding hw/ufs: Emulate DME_GET/SET for PA layer attributes Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
5 daysMerge tag 'pull-target-arm-20260629' of https://gitlab.com/pm215/qemu into ↵Stefan Hajnoczi
staging target-arm queue: * hw/timer/imx_epit: Replace DPRINTF with trace events target/arm: Enable SCTLR_EL1.EnFPM for user-only target/arm: Implement FEAT_SME_F8F32 target/arm: Implement FEAT_SSVE_AES target/arm: Implement FEAT_SME_F8F16 target/arm: GICv5: Fix some minor bugs target/arm: Add GPC3 granule bypass windows target/arm: Fix some minor timer related bugs hw/arm/sabrelite: Add FlexCAN emulation docs/system: add FEAT_ECV_POFF to the emulation list docs/system/arm/virt: Document accelerated SMMUv3 and Tegra241 CMDQV # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmpCXaQZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3nfkEACJkoMzHDyHcAiRdO8fK4o6 # zHP3f42UOnXTbX//Yga0PpxScWfvD8XbbOSeJRvpjuxl8nP8QF4/rF4b+atMy9Vl # MH0r/CWl9fZwQOSmjOLzgRGzXx0j9RPPpB/7eYTnKYImfOaEEaGvW4JqoBRE2Nbo # x5PaQjaqFQi76uGAJvALPgAPCgaK1DGbNDSRuH4RM7auLBWmSaoxdidiTDSBUqY0 # xsI/lU7t+/LLWirjP/QhM4mbxEc2DjENbguRHYlOqe5aHc6KdSmNj2B4/hTfyDON # c6APaAAPfCy3duL3JsvmwRZ8YM7zoUFEHysLjRxLWyiFfXZUIXPSMZaGpz88iyDV # Cbraw24K5tVVNvwQTKOpHYCnjNb4dZj1Zt/jdGIu16LQ8nsKgX2EJ6oh6lI85Q6n # d3Jbq+iLOy2r2r4CRTMIJYKZ2Bikkmyr+wZGO18nttnTVpWNzWVZtq4cutygr5vb # 0+5Lmr7YeYsdmIc1tpcJmlfmmo7dW987HyzK3/B65gPXV64w+a3eALRLPkMGevTT # MhG48151NEovHxfKqzsOMIixnPUKGPtAUbeKy/Ywv2ezKUmER19h/7nJ0lsa32pl # HYctGj4QeK4VjOO8E1q44ZIionhZFt+RHXBxxbiBzQBns/ryFBOQFEA3WzKi7rnd # a0v1M+AAK/UxmCjV7Sl0WA== # =OvGk # -----END PGP SIGNATURE----- # gpg: Signature made Mon 29 Jun 2026 13:57:24 CEST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20260629' of https://gitlab.com/pm215/qemu: (54 commits) docs/system/arm/virt: Document accelerated SMMUv3 and Tegra241 CMDQV target/arm: Enable FEAT_SME_F8F16 for -cpu max target/arm: Implement FVDOT (FP8 to FP16) target/arm: Rename FVDOT pattern target/arm: Implement FMOPA (widening, 2-way, FP8 to FP16) target/arm: Implement FDOT (multiple and indexed, FP8 to FP16) target/arm: Implement FDOT (multiple, multiple and single, FP8 to FP16) target/arm: Implement FMLAL (multiple and indexed, FP8 to FP16) target/arm: Implement FMLAL (multiple, multiple and single, FP8 to FP16) target/arm: Rename SME FMLAL/FMLSL patterns target/arm: Enable FADD/FSUB (half-precision) with FEAT_SME_F8F16 docs/system: add FEAT_ECV_POFF to the emulation list target/arm: trigger timer recalc on HCR:(E2H|TGE) changes target/arm: gate check on scr_el3 behind ARM_FEATURE_EL3 check target/arm: trigger timer recalc on SCR:ECVEN change target/arm: trigger timer recalculation when toggling CNTHCTL:ECV target/arm: split evaluation of CNTHCTL timer IRQ masks docs/arm/sabrelite: Mention FlexCAN support tests: Add qtests for FlexCAN hw/arm: Plug FlexCAN into FSL_IMX6 and Sabrelite ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
6 dayshw/riscv/riscv-iommu.c: always fault with SADE=0 and A=0Daniel Henrique Barboza
riscv-iommu spec: "If SADE is 1, the IOMMU updates A and D bits in first-stage PTEs atomically. If SADE is 0, the IOMMU causes a page-fault corresponding to the original access type if the A bit is 0 or if the memory access is a store and the D bit is 0.". Note that SADE=0 and A=0 will always cause a fault regardless of the original access type. Right now we're faulting in this case just for reads. Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3551 Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Message-ID: <20260630211044.82894-1-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/riscv/atlantis: Add some i2c peripheralsJoel Stanley
Add an I2C RTC device and a temperature sensor. These are not present on the board but help for testing. The tmp105 is a lm75 compatible temperature sensor used by the SENSORS_LM75 Linux kernel driver. The ds1338 is a RTC device that is used by the RTC_DRV_DS1307 Linux kernel driver. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20260630024952.1520546-13-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/riscv/atlantis: Integrate i2c controllersJoel Stanley
Add DesignWare I2C controllers to the tt-atlantis machine. Provide a fixed clock in the device tree so that the Linux driver probes without WARNing. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20260630024952.1520546-12-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/i2c: Add DesignWare I2C ControllerChris Rauer
Add a model for the Synopsys DesignWare Advanced I2C/SMBus Controller with sufficient functionality to be used by the Linux Designware I2C platform driver. This IP is used in the Tenstorrent Atlantis RISC-V SoC and will be added to the QEMU tt-atlantis machine. [npiggin: changelog, code cleanups and fixes as-per below link] Reviewed-by: Hao Wu <wuhaotsh@google.com> Signed-off-by: Chris Rauer <crauer@google.com> Link: https://lore.kernel.org/qemu-devel/20220110214755.810343-2-venture@google.com [jms: rebase and minor build fixes for class_init and reset callback] Link: https://lore.kernel.org/qemu-devel/20260507120524.111056-1-npiggin@gmail.com Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Corey Minyard <cminyard@mvista.com> Tested-by: Alano Song <AlanoSong@163.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20260630024952.1520546-11-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 daystests/functional/riscv64: Add tt-atlantis testsNicholas Piggin
Add OpenSBI and Linux boot tests for the tt-atlantis machine. Based on tests/functional/riscv64/test_sifive_u.py. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20260630024952.1520546-10-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/riscv/atlantis: Ensure OpenSBI has a non-zero next_addrAlistair Francis
When using OpenSBI fw_dynamic on the Atlantis board OpenSBI fails to print any output, as it hits an error early on in the boot process and gets stuck in `sbi_hart_hang()`. The error occurs in the `sanitize_domain()` function inside OpenSBI. `sanitize_domain()` is called after a M-Mode OpenSBI Firmware and a generic coverall S-Mode RWX memory region are created. `sanitize_domain()` is checking that the next address is executable. If no next address is provided (which occurs on QEMU with an empty payload), then `dom->next_addr` will be 0. On most RISC-V boards address 0 will fall inside the coverall S-Mode RWX memory region and pass this check. On Atlantis the OpenSBI firmware is running at address 0, so this address falls inside the M-Mode only OpenSBI firmware region and fails the check. Once the check has failed OpenSBI aborts and the user doesn't see any messages. This can be fixed by either supplying a payload, or just manually forcing a non-zero address (actually just any address that isn't the OpenSBI firmware) for next_addr. This patch ensures that if no kernel is loaded we still specify a default kernel_entry so that OpenSBI happily boots and jumps to the first address in memory. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260630024952.1520546-9-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/riscv: Add Tenstorrent Atlantis machineJoel Stanley
The Tenstorrent Atlantis platform is a collaboration between Tenstorrent and CoreLab Technology. It is based on the Atlantis SoC, which includes the Ascalon-X CPU and other IP from Tenstorrent and CoreLab Technology. The Tenstorrent Ascalon-X is a high performance 64-bit RVA23 compliant RISC-V CPU. Add the tt-atlantis machine containing serial console, interrupt controllers, and device tree support. The Atlantis boot images loaded from include OpenSBI and an initial DTB that is passed to OpenSBI. This is approximated in the model by having QEMU build the device tree rather than load a DTB image directly. Subsequent stages may use the modified DTB provided by OpenSBI or opt to supply their own. qemu-system-riscv64 -M tt-atlantis -m 512M \ -kernel Image -initrd rootfs.cpio -nographic Co-Developed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260630024952.1520546-8-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 daystarget/riscv: tt-ascalon: Enable Zkr extensionNicholas Piggin
Ascalon supports Zkr and the SEED CSR. Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20260630024952.1520546-7-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/riscv/aia: Configure stride for the M-mode IMSICJoel Stanley
riscv_create_aia() currently hard-codes the M-IMSIC at one 4 KiB page per hart and gives callers no way to widen it. Add an m_imsic_stride parameter that supplies the per hart byte stride directly. The virt machine passes IMSIC_HART_SIZE(0) (= 4 KiB), preserving its existing compact layout. The parameter only changes how the slots are spaced, with the rest of each slot reserved. This allows future platforms that have different layouts to control the stride. Reviewed-by: Philippe Mathieu-Daudé <philmd@mailo.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20260630024952.1520546-6-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/riscv/aia: Provide number of irq sourcesJoel Stanley
Instead of hard coding the number of IRQ sources used by the APLIC pass it in as a parameter. This allows other machines to configure this as required. The maximum number of sources is 1023. Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20260630024952.1520546-5-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/riscv/virt: Move AIA initialisation to helper fileJoel Stanley
The AIA init will be used by any server class riscv machine. Separate it out in order to share code with such systems. The virt machine keeps machine specific #defines such as VIRT_IRQCHIP_NUM_MSIS, VIRT_IRQCHIP_NUM_PRIO_BITS. Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20260630024952.1520546-4-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/riscv/boot: Account for discontiguous memory when loading firmwareNicholas Piggin
This loads firmware into the first (low) memory range, accounting for machines having discontiguous memory regions. Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20260630024952.1520546-3-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/riscv/boot: Describe discontiguous memory in boot_infoNicholas Piggin
Machines that have discontiguous memory may need to adjust where firmware and images are loaded at boot. Provide an interface for machines to describe a discontiguous low/high RAM scheme for this purpose. Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20260630024952.1520546-2-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 daystarget/riscv: Check PMP before updating PTEInochi Amaoto
According to the RISC-V spec, the PTE update is a supervisor write operations, and it should also follow the CPU PMP configuration like the PTE read. Cc: qemu-stable@nongnu.org Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260622113402.563196-1-inochiama@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 daystarget/riscv: Report QEMU CPU archid as 42Charlie Jenkins
When a non-vendor CPU is used, report the archid as 42 which has been allocated for QEMU in the riscv isa manual [1]. This can help software check if it is running in QEMU. [1] https://github.com/riscv/riscv-isa-manual/blob/main/marchid.md Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Message-ID: <20260625-marchid-v2-1-3821c351028b@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/riscv/riscv-iommu.c: fix MSI MRIF interrupt-pending offsetDaniel Henrique Barboza
We're doing a wrong shift when calculating the offset for the interrupt-pending bits, off by one right shift order. This went undercover for awhile because the calculation works for interrupt entities 1 to 63. The math goes wrong when using interrupt entities 64 or greater. Instead of fixing the issue and running we're also adding some notes on where this calc comes from. Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3561 Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260626220529.3800372-1-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/riscv/riscv-iommu.c: set RISCV_IOMMU_FQ_HDR_PV appropriatelyDaniel Henrique Barboza
We're hardcoding 'true' to FQ_HDR_PV in riscv_iommu_report_fault(). Use the 'pv' bool the caller provides that indicates if the process_id is valid. Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3556 Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260626173341.3661446-1-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/riscv/riscv-iommu: set cmd_ill IOFENCE.C rsvp bits are setDaniel Henrique Barboza
We're not setting RISCV_IOMMU_CQCSR_CMD_ILL if a reserved bit happens to be set in an IOFENCE.C command. Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3575 Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260626170533.3562484-1-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 daystarget/riscv: Apply UXL WARL handling to vsstatusSeungJu Cheon
write_mstatus() already handles the reserved UXL value by writing a legal value instead. Apply the same handling when writing vsstatus so that reserved UXL values follow the same WARL behavior. Factor the common logic into a local helper riscv_write_uxl() and use it for both mstatus and vsstatus. Suggested-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Fixes: f310df58bd2 ("target/riscv: Enable uxl field write") Signed-off-by: SeungJu Cheon <suunj1331@gmail.com> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Message-ID: <20260625081521.595683-1-suunj1331@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/riscv/riscv-iommu: check DC.TC reserved bitsDaniel Henrique Barboza
We are not checking for reserved TC bits being set during device context validation. Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3548 Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260627194640.4130073-1-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/riscv/riscv-iommu.c: make FCTL.BE read only 0Daniel Henrique Barboza
We do not support FCTL.BE equal to 1 hence do not allow this bit to be set by software. While we're at it: the riscv-iommu spec allows FCTL.GXL to be set freely and we do not have hardcoded restrictions on it, so make it writable. Fixes: 0c54acb824 ("hw/riscv: add RISC-V IOMMU base emulation") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3576 Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260625210833.3294437-3-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/riscv/riscv-iommu: rename regs_rw to regsDaniel Henrique Barboza
The existing nomenclature can be misleading: regs_rw can cosplay as 'read and write' mask, in particular because we have regs_ro which is a read only mask. regs_rw is the current reg value, and all bits that aren't on the regs_ro mask is considered r/w bits. Rename regs_rw to 'regs' to be on par with the nomenclature other devices uses (e.g. cadence_gem). Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260625210833.3294437-2-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/riscv: add create_fdt_plic() helperDaniel Henrique Barboza
Consolidate the common plic FDT code between 'virt' and sifive_u boards into a single place. Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260616235939.1358663-6-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/riscv/virt.c: change 'plic' nodename to 'interrupt-controller'Daniel Henrique Barboza
We're still using "/soc/plic@..." as FDT nodename in virt.c. This is not the right nodename per the DT docs: https://www.kernel.org/doc/Documentation/devicetree/bindings/interrupt-controller/sifive%2Cplic-1.0.0.txt The nodename must be 'interrupt-controller@...' since the node inherits the 'interrupt-controller' type. In fact, ever since at least the 2020 Linux kernel commit c825a081c169cc7f ("dt-bindings: riscv: convert plic bindings to json-schema") the correct nodename has been 'interrupt-controller' for the sifive PLIC controller. There's no deprecation needed for bug fixes so we're just fixing the name. This was the policy we dud when fixing the aplic [1] and the imsic [2] nodenames to 'interrupt-controller@...' as well. The sifive_u PLIC FDT already uses the correct nodename for PLIC, so it is safe to assume that available SW is already aware of the correct nodename and this change won't affect well-behaved SW. [1] commit 29390fd ("hw/riscv/virt.c: rename aplic nodename to 'interrupt-controller'") [2] commit e8ad581 ("hw/riscv/virt.c: change imsic nodename to 'interrupt-controller'") Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260616235939.1358663-5-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/riscv/sifive_u: add #address-cells in PLIC FDTDaniel Henrique Barboza
By Linux FDT docs in [1] the "address-cells" property is mandatory. Set it to zero. While we're at it let's also put this new value and the interrupt-cells value in macros, like the 'virt' board is doing. [1] https://www.kernel.org/doc/Documentation/devicetree/bindings/interrupt-controller/sifive%2Cplic-1.0.0.txt Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260616235939.1358663-4-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 dayshw/riscv/sifive_u.c: use intc_phandle in plic creationDaniel Henrique Barboza
The info about intc_phandles for each CPU is already stored in the intc_phandles array. We don't need to fetch them again using qemu_fdt_get_phandle(). Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260616235939.1358663-3-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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